1; RUN: llc -march=hexagon < %s 2; REQUIRES: asserts 3 4target triple = "hexagon" 5 6@g0 = common global <16 x i32> zeroinitializer, align 64 7@g1 = common global <32 x i32> zeroinitializer, align 128 8@g2 = common global <32 x i32> zeroinitializer, align 128 9 10; Function Attrs: nounwind 11define void @f0() #0 { 12b0: 13 %v0 = load <16 x i32>, <16 x i32>* @g0, align 64 14 %v1 = load <32 x i32>, <32 x i32>* @g1, align 128 15 %v2 = call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v1) 16 %v3 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v0, <16 x i32> %v2) 17 store <32 x i32> %v3, <32 x i32>* @g2, align 128 18 ret void 19} 20 21; Function Attrs: nounwind readnone 22declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 23 24; Function Attrs: nounwind readnone 25declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1 26 27attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 28attributes #1 = { nounwind readnone } 29