1; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s 2; CHECK: = vmem(r{{[0-9]+}}++#1) 3 4target triple = "hexagon-unknown--elf" 5 6declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0 7declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #0 8declare <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32>) #0 9declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0 10declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0 11declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0 12declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0 13 14define void @f0(i8* %a0, <32 x i32>* %a1) #1 { 15b0: 16 br label %b1 17 18b1: ; preds = %b2, %b1 19 %v0 = phi <128 x i8> [ %v7, %b1 ], [ undef, %b0 ] 20 %v1 = phi i32 [ %v19, %b1 ], [ 0, %b0 ] 21 %v2 = add nsw i32 %v1, undef 22 %v3 = shl i32 %v2, 7 23 %v4 = add nsw i32 %v3, 128 24 %v5 = getelementptr inbounds i8, i8* %a0, i32 %v4 25 %v6 = bitcast i8* %v5 to <128 x i8>* 26 %v7 = load <128 x i8>, <128 x i8>* %v6, align 128 27 %v8 = bitcast <128 x i8> %v0 to <32 x i32> 28 %v9 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %v8, i32 1) 29 %v10 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %v9) #1 30 %v11 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v10) #1 31 %v12 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %v11, <64 x i32> undef) #1 32 %v13 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v12) 33 %v14 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %v13) #1 34 %v15 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v14, <32 x i32> undef) 35 %v16 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v15) #1 36 %v17 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v16) #1 37 %v18 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %v17, <32 x i32> undef) #1 38 store <32 x i32> %v18, <32 x i32>* %a1, align 128 39 %v19 = add nuw nsw i32 %v1, 1 40 br label %b1 41} 42 43declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 44 45attributes #0 = { nounwind readnone } 46attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } 47