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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3
4; Test custom lowering for 32-bit integer multiplication.
5
6target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
7target triple = "lanai"
8
9define i32 @f6(i32 inreg %a) #0 {
10; CHECK-LABEL: f6:
11; CHECK:       ! %bb.0:
12; CHECK-NEXT:    st %fp, [--%sp]
13; CHECK-NEXT:    add %sp, 0x8, %fp
14; CHECK-NEXT:    sub %sp, 0x8, %sp
15; CHECK-NEXT:    sh %r6, 0x1, %r3
16; CHECK-NEXT:    sh %r6, 0x3, %r9
17; CHECK-NEXT:    sub %r9, %r3, %rv
18; CHECK-NEXT:    ld -4[%fp], %pc ! return
19; CHECK-NEXT:    add %fp, 0x0, %sp
20; CHECK-NEXT:    ld -8[%fp], %fp
21  %1 = mul nsw i32 %a, 6
22  ret i32 %1
23}
24
25define i32 @f7(i32 inreg %a) #0 {
26; CHECK-LABEL: f7:
27; CHECK:       ! %bb.0:
28; CHECK-NEXT:    st %fp, [--%sp]
29; CHECK-NEXT:    add %sp, 0x8, %fp
30; CHECK-NEXT:    sub %sp, 0x8, %sp
31; CHECK-NEXT:    sh %r6, 0x3, %r3
32; CHECK-NEXT:    sub %r3, %r6, %rv
33; CHECK-NEXT:    ld -4[%fp], %pc ! return
34; CHECK-NEXT:    add %fp, 0x0, %sp
35; CHECK-NEXT:    ld -8[%fp], %fp
36  %1 = mul nsw i32 %a, 7
37  ret i32 %1
38}
39
40define i32 @f8(i32 inreg %a) #0 {
41; CHECK-LABEL: f8:
42; CHECK:       ! %bb.0:
43; CHECK-NEXT:    st %fp, [--%sp]
44; CHECK-NEXT:    add %sp, 0x8, %fp
45; CHECK-NEXT:    sub %sp, 0x8, %sp
46; CHECK-NEXT:    sh %r6, 0x3, %rv
47; CHECK-NEXT:    ld -4[%fp], %pc ! return
48; CHECK-NEXT:    add %fp, 0x0, %sp
49; CHECK-NEXT:    ld -8[%fp], %fp
50  %1 = shl nsw i32 %a, 3
51  ret i32 %1
52}
53
54define i32 @f9(i32 inreg %a) #0 {
55; CHECK-LABEL: f9:
56; CHECK:       ! %bb.0:
57; CHECK-NEXT:    st %fp, [--%sp]
58; CHECK-NEXT:    add %sp, 0x8, %fp
59; CHECK-NEXT:    sub %sp, 0x8, %sp
60; CHECK-NEXT:    sh %r6, 0x3, %r3
61; CHECK-NEXT:    add %r3, %r6, %rv
62; CHECK-NEXT:    ld -4[%fp], %pc ! return
63; CHECK-NEXT:    add %fp, 0x0, %sp
64; CHECK-NEXT:    ld -8[%fp], %fp
65  %1 = mul nsw i32 %a, 9
66  ret i32 %1
67}
68
69define i32 @f10(i32 inreg %a) #0 {
70; CHECK-LABEL: f10:
71; CHECK:       ! %bb.0:
72; CHECK-NEXT:    st %fp, [--%sp]
73; CHECK-NEXT:    add %sp, 0x8, %fp
74; CHECK-NEXT:    sub %sp, 0x8, %sp
75; CHECK-NEXT:    sh %r6, 0x1, %r3
76; CHECK-NEXT:    sh %r6, 0x3, %r9
77; CHECK-NEXT:    add %r9, %r3, %rv
78; CHECK-NEXT:    ld -4[%fp], %pc ! return
79; CHECK-NEXT:    add %fp, 0x0, %sp
80; CHECK-NEXT:    ld -8[%fp], %fp
81  %1 = mul nsw i32 %a, 10
82  ret i32 %1
83}
84
85define i32 @f1280(i32 inreg %a) #0 {
86; CHECK-LABEL: f1280:
87; CHECK:       ! %bb.0:
88; CHECK-NEXT:    st %fp, [--%sp]
89; CHECK-NEXT:    add %sp, 0x8, %fp
90; CHECK-NEXT:    sub %sp, 0x8, %sp
91; CHECK-NEXT:    sh %r6, 0x8, %r3
92; CHECK-NEXT:    sh %r6, 0xa, %r9
93; CHECK-NEXT:    add %r9, %r3, %rv
94; CHECK-NEXT:    ld -4[%fp], %pc ! return
95; CHECK-NEXT:    add %fp, 0x0, %sp
96; CHECK-NEXT:    ld -8[%fp], %fp
97  %1 = mul nsw i32 %a, 1280
98  ret i32 %1
99}
100
101define i32 @fm6(i32 inreg %a) #0 {
102; CHECK-LABEL: fm6:
103; CHECK:       ! %bb.0:
104; CHECK-NEXT:    st %fp, [--%sp]
105; CHECK-NEXT:    add %sp, 0x8, %fp
106; CHECK-NEXT:    sub %sp, 0x8, %sp
107; CHECK-NEXT:    sh %r6, 0x3, %r3
108; CHECK-NEXT:    sh %r6, 0x1, %r9
109; CHECK-NEXT:    sub %r9, %r3, %rv
110; CHECK-NEXT:    ld -4[%fp], %pc ! return
111; CHECK-NEXT:    add %fp, 0x0, %sp
112; CHECK-NEXT:    ld -8[%fp], %fp
113  %1 = mul nsw i32 %a, -6
114  ret i32 %1
115}
116
117define i32 @fm7(i32 inreg %a) #0 {
118; CHECK-LABEL: fm7:
119; CHECK:       ! %bb.0:
120; CHECK-NEXT:    st %fp, [--%sp]
121; CHECK-NEXT:    add %sp, 0x8, %fp
122; CHECK-NEXT:    sub %sp, 0x8, %sp
123; CHECK-NEXT:    sh %r6, 0x3, %r3
124; CHECK-NEXT:    sub %r6, %r3, %rv
125; CHECK-NEXT:    ld -4[%fp], %pc ! return
126; CHECK-NEXT:    add %fp, 0x0, %sp
127; CHECK-NEXT:    ld -8[%fp], %fp
128  %1 = mul nsw i32 %a, -7
129  ret i32 %1
130}
131
132define i32 @fm8(i32 inreg %a) #0 {
133; CHECK-LABEL: fm8:
134; CHECK:       ! %bb.0:
135; CHECK-NEXT:    st %fp, [--%sp]
136; CHECK-NEXT:    add %sp, 0x8, %fp
137; CHECK-NEXT:    sub %sp, 0x8, %sp
138; CHECK-NEXT:    sh %r6, 0x3, %r3
139; CHECK-NEXT:    sub %r0, %r3, %rv
140; CHECK-NEXT:    ld -4[%fp], %pc ! return
141; CHECK-NEXT:    add %fp, 0x0, %sp
142; CHECK-NEXT:    ld -8[%fp], %fp
143  %1 = mul nsw i32 %a, -8
144  ret i32 %1
145}
146
147define i32 @fm9(i32 inreg %a) #0 {
148; CHECK-LABEL: fm9:
149; CHECK:       ! %bb.0:
150; CHECK-NEXT:    st %fp, [--%sp]
151; CHECK-NEXT:    add %sp, 0x8, %fp
152; CHECK-NEXT:    sub %sp, 0x8, %sp
153; CHECK-NEXT:    sh %r6, 0x3, %r3
154; CHECK-NEXT:    add %r6, %r3, %r3
155; CHECK-NEXT:    sub %r0, %r3, %rv
156; CHECK-NEXT:    ld -4[%fp], %pc ! return
157; CHECK-NEXT:    add %fp, 0x0, %sp
158; CHECK-NEXT:    ld -8[%fp], %fp
159  %1 = mul nsw i32 %a, -9
160  ret i32 %1
161}
162
163define i32 @fm10(i32 inreg %a) #0 {
164; CHECK-LABEL: fm10:
165; CHECK:       ! %bb.0:
166; CHECK-NEXT:    st %fp, [--%sp]
167; CHECK-NEXT:    add %sp, 0x8, %fp
168; CHECK-NEXT:    sub %sp, 0x8, %sp
169; CHECK-NEXT:    sh %r6, 0x3, %r3
170; CHECK-NEXT:    sh %r6, 0x1, %r9
171; CHECK-NEXT:    add %r9, %r3, %r3
172; CHECK-NEXT:    sub %r0, %r3, %rv
173; CHECK-NEXT:    ld -4[%fp], %pc ! return
174; CHECK-NEXT:    add %fp, 0x0, %sp
175; CHECK-NEXT:    ld -8[%fp], %fp
176  %1 = mul nsw i32 %a, -10
177  ret i32 %1
178}
179
180define i32 @h1(i32 inreg %a) #0 {
181; CHECK-LABEL: h1:
182; CHECK:       ! %bb.0:
183; CHECK-NEXT:    st %fp, [--%sp]
184; CHECK-NEXT:    add %sp, 0x8, %fp
185; CHECK-NEXT:    sub %sp, 0x8, %sp
186; CHECK-NEXT:    mov 0xaaaa0000, %r3
187; CHECK-NEXT:    add %pc, 0x10, %rca
188; CHECK-NEXT:    st %rca, [--%sp]
189; CHECK-NEXT:    bt __mulsi3
190; CHECK-NEXT:    or %r3, 0xaaab, %r7
191; CHECK-NEXT:    ld -4[%fp], %pc ! return
192; CHECK-NEXT:    add %fp, 0x0, %sp
193; CHECK-NEXT:    ld -8[%fp], %fp
194  %1 = mul i32 %a, -1431655765
195  ret i32 %1
196}
197