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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
3# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
4--- |
5
6  define void @bitreverse_i32() { entry: ret void }
7  define void @bitreverse_i64() { entry: ret void }
8
9...
10---
11name:            bitreverse_i32
12alignment:       4
13tracksRegLiveness: true
14body:             |
15  bb.1.entry:
16    liveins: $a0
17
18    ; MIPS32-LABEL: name: bitreverse_i32
19    ; MIPS32: liveins: $a0
20    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
21    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
22    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
23    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
24    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
25    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
26    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
27    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
28    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
29    ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
30    ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
31    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
32    ; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
33    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
34    ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
35    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
36    ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
37    ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
38    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]]
39    ; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND3]]
40    ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
41    ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
42    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]]
43    ; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C5]](s32)
44    ; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32)
45    ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]]
46    ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]]
47    ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
48    ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
49    ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]]
50    ; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
51    ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
52    ; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
53    ; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND7]]
54    ; MIPS32: $v0 = COPY [[OR5]](s32)
55    ; MIPS32: RetRA implicit $v0
56    ; MIPS32R2-LABEL: name: bitreverse_i32
57    ; MIPS32R2: liveins: $a0
58    ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
59    ; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
60    ; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
61    ; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
62    ; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
63    ; MIPS32R2: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
64    ; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
65    ; MIPS32R2: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
66    ; MIPS32R2: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[AND1]]
67    ; MIPS32R2: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
68    ; MIPS32R2: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
69    ; MIPS32R2: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]]
70    ; MIPS32R2: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
71    ; MIPS32R2: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32)
72    ; MIPS32R2: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]]
73    ; MIPS32R2: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND3]]
74    ; MIPS32R2: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
75    ; MIPS32R2: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
76    ; MIPS32R2: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
77    ; MIPS32R2: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C4]](s32)
78    ; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
79    ; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
80    ; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND5]]
81    ; MIPS32R2: $v0 = COPY [[OR2]](s32)
82    ; MIPS32R2: RetRA implicit $v0
83    %0:_(s32) = COPY $a0
84    %1:_(s32) = G_BITREVERSE %0
85    $v0 = COPY %1(s32)
86    RetRA implicit $v0
87
88...
89---
90name:            bitreverse_i64
91alignment:       4
92tracksRegLiveness: true
93body:             |
94  bb.1.entry:
95    liveins: $a0, $a1
96
97    ; MIPS32-LABEL: name: bitreverse_i64
98    ; MIPS32: liveins: $a0, $a1
99    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
100    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
101    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
102    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
103    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
104    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
105    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
106    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
107    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
108    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
109    ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
110    ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
111    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
112    ; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
113    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
114    ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
115    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
116    ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
117    ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
118    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]]
119    ; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND3]]
120    ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
121    ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
122    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]]
123    ; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C5]](s32)
124    ; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32)
125    ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]]
126    ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]]
127    ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
128    ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
129    ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]]
130    ; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
131    ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
132    ; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
133    ; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND7]]
134    ; MIPS32: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
135    ; MIPS32: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
136    ; MIPS32: [[OR6:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL5]]
137    ; MIPS32: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
138    ; MIPS32: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C2]](s32)
139    ; MIPS32: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL6]]
140    ; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
141    ; MIPS32: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
142    ; MIPS32: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[AND9]]
143    ; MIPS32: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR8]], [[C4]]
144    ; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C3]](s32)
145    ; MIPS32: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[OR8]], [[C3]](s32)
146    ; MIPS32: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SHL7]], [[C4]]
147    ; MIPS32: [[OR9:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[AND11]]
148    ; MIPS32: [[AND12:%[0-9]+]]:_(s32) = G_AND [[OR9]], [[C6]]
149    ; MIPS32: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[C5]](s32)
150    ; MIPS32: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[OR9]], [[C5]](s32)
151    ; MIPS32: [[AND13:%[0-9]+]]:_(s32) = G_AND [[SHL8]], [[C6]]
152    ; MIPS32: [[OR10:%[0-9]+]]:_(s32) = G_OR [[LSHR8]], [[AND13]]
153    ; MIPS32: [[AND14:%[0-9]+]]:_(s32) = G_AND [[OR10]], [[C8]]
154    ; MIPS32: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[C7]](s32)
155    ; MIPS32: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[OR10]], [[C7]](s32)
156    ; MIPS32: [[AND15:%[0-9]+]]:_(s32) = G_AND [[SHL9]], [[C8]]
157    ; MIPS32: [[OR11:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[AND15]]
158    ; MIPS32: $v0 = COPY [[OR5]](s32)
159    ; MIPS32: $v1 = COPY [[OR11]](s32)
160    ; MIPS32: RetRA implicit $v0, implicit $v1
161    ; MIPS32R2-LABEL: name: bitreverse_i64
162    ; MIPS32R2: liveins: $a0, $a1
163    ; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
164    ; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
165    ; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
166    ; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
167    ; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
168    ; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
169    ; MIPS32R2: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
170    ; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
171    ; MIPS32R2: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
172    ; MIPS32R2: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[AND1]]
173    ; MIPS32R2: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
174    ; MIPS32R2: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
175    ; MIPS32R2: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]]
176    ; MIPS32R2: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
177    ; MIPS32R2: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32)
178    ; MIPS32R2: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]]
179    ; MIPS32R2: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND3]]
180    ; MIPS32R2: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
181    ; MIPS32R2: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
182    ; MIPS32R2: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
183    ; MIPS32R2: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C4]](s32)
184    ; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
185    ; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
186    ; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND5]]
187    ; MIPS32R2: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
188    ; MIPS32R2: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BSWAP1]], [[C1]]
189    ; MIPS32R2: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C]](s32)
190    ; MIPS32R2: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[BSWAP1]], [[C]](s32)
191    ; MIPS32R2: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C1]]
192    ; MIPS32R2: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND7]]
193    ; MIPS32R2: [[AND8:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C3]]
194    ; MIPS32R2: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[C2]](s32)
195    ; MIPS32R2: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C2]](s32)
196    ; MIPS32R2: [[AND9:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C3]]
197    ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]]
198    ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]]
199    ; MIPS32R2: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C4]](s32)
200    ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
201    ; MIPS32R2: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SHL5]], [[C5]]
202    ; MIPS32R2: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[AND11]]
203    ; MIPS32R2: $v0 = COPY [[OR2]](s32)
204    ; MIPS32R2: $v1 = COPY [[OR5]](s32)
205    ; MIPS32R2: RetRA implicit $v0, implicit $v1
206    %1:_(s32) = COPY $a0
207    %2:_(s32) = COPY $a1
208    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
209    %3:_(s64) = G_BITREVERSE %0
210    %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
211    $v0 = COPY %4(s32)
212    $v1 = COPY %5(s32)
213    RetRA implicit $v0, implicit $v1
214
215...
216