1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 3--- | 4 5 define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void} 6 define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void} 7 define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void} 8 define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void} 9 define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void} 10 define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void} 11 define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void} 12 define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void} 13 define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void} 14 define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void} 15 16... 17--- 18name: load1_s8_to_zextLoad1_s32 19alignment: 4 20tracksRegLiveness: true 21body: | 22 bb.1.entry: 23 liveins: $a0 24 25 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32 26 ; MIPS32: liveins: $a0 27 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 28 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 29 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 30 ; MIPS32: RetRA implicit $v0 31 %0:_(p0) = COPY $a0 32 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.px) 33 $v0 = COPY %2(s32) 34 RetRA implicit $v0 35 36... 37--- 38name: load2_s16_to_zextLoad2_s32 39alignment: 4 40tracksRegLiveness: true 41body: | 42 bb.1.entry: 43 liveins: $a0 44 45 ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32 46 ; MIPS32: liveins: $a0 47 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 48 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px) 49 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 50 ; MIPS32: RetRA implicit $v0 51 %0:_(p0) = COPY $a0 52 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.px) 53 $v0 = COPY %2(s32) 54 RetRA implicit $v0 55 56... 57--- 58name: load1_s8_to_zextLoad1_s16 59alignment: 4 60tracksRegLiveness: true 61body: | 62 bb.1.entry: 63 liveins: $a0 64 65 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16 66 ; MIPS32: liveins: $a0 67 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 68 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 69 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32) 70 ; MIPS32: $v0 = COPY [[COPY1]](s32) 71 ; MIPS32: RetRA implicit $v0 72 %0:_(p0) = COPY $a0 73 %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.px) 74 %3:_(s32) = G_ANYEXT %2(s16) 75 $v0 = COPY %3(s32) 76 RetRA implicit $v0 77 78... 79--- 80name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32 81alignment: 4 82tracksRegLiveness: true 83body: | 84 bb.1.entry: 85 liveins: $a0 86 87 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32 88 ; MIPS32: liveins: $a0 89 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 90 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 91 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 92 ; MIPS32: RetRA implicit $v0 93 %0:_(p0) = COPY $a0 94 %3:_(s32) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.px) 95 $v0 = COPY %3(s32) 96 RetRA implicit $v0 97 98... 99--- 100name: load4_s32_to_zextLoad4_s64 101alignment: 4 102tracksRegLiveness: true 103body: | 104 bb.1.entry: 105 liveins: $a0 106 107 ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64 108 ; MIPS32: liveins: $a0 109 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 110 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px) 111 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 112 ; MIPS32: $v0 = COPY [[LOAD]](s32) 113 ; MIPS32: $v1 = COPY [[C]](s32) 114 ; MIPS32: RetRA implicit $v0, implicit $v1 115 %0:_(p0) = COPY $a0 116 %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.px) 117 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) 118 $v0 = COPY %3(s32) 119 $v1 = COPY %4(s32) 120 RetRA implicit $v0, implicit $v1 121 122... 123--- 124name: load1_s8_to_sextLoad1_s32 125alignment: 4 126tracksRegLiveness: true 127body: | 128 bb.1.entry: 129 liveins: $a0 130 131 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32 132 ; MIPS32: liveins: $a0 133 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 134 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 135 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 136 ; MIPS32: RetRA implicit $v0 137 %0:_(p0) = COPY $a0 138 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.px) 139 $v0 = COPY %2(s32) 140 RetRA implicit $v0 141 142... 143--- 144name: load2_s16_to_sextLoad2_s32 145alignment: 4 146tracksRegLiveness: true 147body: | 148 bb.1.entry: 149 liveins: $a0 150 151 ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32 152 ; MIPS32: liveins: $a0 153 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 154 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px) 155 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 156 ; MIPS32: RetRA implicit $v0 157 %0:_(p0) = COPY $a0 158 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load 2 from %ir.px) 159 $v0 = COPY %2(s32) 160 RetRA implicit $v0 161 162... 163--- 164name: load1_s8_to_sextLoad1_s16 165alignment: 4 166tracksRegLiveness: true 167body: | 168 bb.1.entry: 169 liveins: $a0 170 171 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16 172 ; MIPS32: liveins: $a0 173 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 174 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 175 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32) 176 ; MIPS32: $v0 = COPY [[COPY1]](s32) 177 ; MIPS32: RetRA implicit $v0 178 %0:_(p0) = COPY $a0 179 %2:_(s16) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.px) 180 %3:_(s32) = G_ANYEXT %2(s16) 181 $v0 = COPY %3(s32) 182 RetRA implicit $v0 183 184... 185--- 186name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32 187alignment: 4 188tracksRegLiveness: true 189body: | 190 bb.1.entry: 191 liveins: $a0 192 193 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32 194 ; MIPS32: liveins: $a0 195 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 196 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 197 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 198 ; MIPS32: RetRA implicit $v0 199 %0:_(p0) = COPY $a0 200 %3:_(s32) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.px) 201 $v0 = COPY %3(s32) 202 RetRA implicit $v0 203 204... 205--- 206name: load4_s32_to_sextLoad4_s64 207alignment: 4 208tracksRegLiveness: true 209body: | 210 bb.1.entry: 211 liveins: $a0 212 213 ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64 214 ; MIPS32: liveins: $a0 215 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 216 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px) 217 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 218 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 219 ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32) 220 ; MIPS32: $v0 = COPY [[LOAD]](s32) 221 ; MIPS32: $v1 = COPY [[ASHR]](s32) 222 ; MIPS32: RetRA implicit $v0, implicit $v1 223 %0:_(p0) = COPY $a0 224 %2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.px) 225 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) 226 $v0 = COPY %3(s32) 227 $v1 = COPY %4(s32) 228 RetRA implicit $v0, implicit $v1 229 230... 231