1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 3 4define i32 @ctpop_i32(i32 %a) { 5; MIPS32-LABEL: ctpop_i32: 6; MIPS32: # %bb.0: # %entry 7; MIPS32-NEXT: srl $1, $4, 1 8; MIPS32-NEXT: lui $2, 21845 9; MIPS32-NEXT: ori $2, $2, 21845 10; MIPS32-NEXT: and $1, $1, $2 11; MIPS32-NEXT: subu $2, $4, $1 12; MIPS32-NEXT: srl $1, $2, 2 13; MIPS32-NEXT: lui $3, 13107 14; MIPS32-NEXT: ori $3, $3, 13107 15; MIPS32-NEXT: and $1, $1, $3 16; MIPS32-NEXT: and $2, $2, $3 17; MIPS32-NEXT: addu $2, $1, $2 18; MIPS32-NEXT: srl $1, $2, 4 19; MIPS32-NEXT: addu $1, $1, $2 20; MIPS32-NEXT: lui $2, 3855 21; MIPS32-NEXT: ori $2, $2, 3855 22; MIPS32-NEXT: and $1, $1, $2 23; MIPS32-NEXT: lui $2, 257 24; MIPS32-NEXT: ori $2, $2, 257 25; MIPS32-NEXT: mul $1, $1, $2 26; MIPS32-NEXT: srl $2, $1, 24 27; MIPS32-NEXT: jr $ra 28; MIPS32-NEXT: nop 29entry: 30 %0 = call i32 @llvm.ctpop.i32(i32 %a) 31 ret i32 %0 32} 33declare i32 @llvm.ctpop.i32(i32) 34 35 36define i64 @ctpop_i64(i64 %a) { 37; MIPS32-LABEL: ctpop_i64: 38; MIPS32: # %bb.0: # %entry 39; MIPS32-NEXT: srl $1, $4, 1 40; MIPS32-NEXT: lui $2, 21845 41; MIPS32-NEXT: ori $7, $2, 21845 42; MIPS32-NEXT: and $1, $1, $7 43; MIPS32-NEXT: subu $2, $4, $1 44; MIPS32-NEXT: srl $1, $2, 2 45; MIPS32-NEXT: lui $3, 13107 46; MIPS32-NEXT: ori $6, $3, 13107 47; MIPS32-NEXT: and $1, $1, $6 48; MIPS32-NEXT: and $2, $2, $6 49; MIPS32-NEXT: addu $2, $1, $2 50; MIPS32-NEXT: srl $1, $2, 4 51; MIPS32-NEXT: addu $1, $1, $2 52; MIPS32-NEXT: lui $2, 3855 53; MIPS32-NEXT: ori $4, $2, 3855 54; MIPS32-NEXT: and $1, $1, $4 55; MIPS32-NEXT: lui $2, 257 56; MIPS32-NEXT: ori $3, $2, 257 57; MIPS32-NEXT: mul $1, $1, $3 58; MIPS32-NEXT: srl $2, $1, 24 59; MIPS32-NEXT: srl $1, $5, 1 60; MIPS32-NEXT: and $1, $1, $7 61; MIPS32-NEXT: subu $5, $5, $1 62; MIPS32-NEXT: srl $1, $5, 2 63; MIPS32-NEXT: and $1, $1, $6 64; MIPS32-NEXT: and $5, $5, $6 65; MIPS32-NEXT: addu $5, $1, $5 66; MIPS32-NEXT: srl $1, $5, 4 67; MIPS32-NEXT: addu $1, $1, $5 68; MIPS32-NEXT: and $1, $1, $4 69; MIPS32-NEXT: mul $1, $1, $3 70; MIPS32-NEXT: srl $1, $1, 24 71; MIPS32-NEXT: addu $2, $1, $2 72; MIPS32-NEXT: ori $3, $zero, 0 73; MIPS32-NEXT: jr $ra 74; MIPS32-NEXT: nop 75entry: 76 %0 = call i64 @llvm.ctpop.i64(i64 %a) 77 ret i64 %0 78} 79declare i64 @llvm.ctpop.i64(i64) 80