1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 3--- | 4 5 define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void} 6 define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void} 7 define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void} 8 define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void} 9 define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void} 10 define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void} 11 define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void} 12 define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void} 13 define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void} 14 define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void} 15 16... 17--- 18name: load1_s8_to_zextLoad1_s32 19alignment: 4 20tracksRegLiveness: true 21body: | 22 bb.1.entry: 23 liveins: $a0 24 25 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32 26 ; MIPS32: liveins: $a0 27 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 28 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 29 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 30 ; MIPS32: RetRA implicit $v0 31 %0:_(p0) = COPY $a0 32 %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px) 33 %2:_(s32) = G_ZEXT %1(s8) 34 $v0 = COPY %2(s32) 35 RetRA implicit $v0 36 37... 38--- 39name: load2_s16_to_zextLoad2_s32 40alignment: 4 41tracksRegLiveness: true 42body: | 43 bb.1.entry: 44 liveins: $a0 45 46 ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32 47 ; MIPS32: liveins: $a0 48 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 49 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px) 50 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 51 ; MIPS32: RetRA implicit $v0 52 %0:_(p0) = COPY $a0 53 %1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px) 54 %2:_(s32) = G_ZEXT %1(s16) 55 $v0 = COPY %2(s32) 56 RetRA implicit $v0 57 58... 59--- 60name: load1_s8_to_zextLoad1_s16 61alignment: 4 62tracksRegLiveness: true 63body: | 64 bb.1.entry: 65 liveins: $a0 66 67 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16 68 ; MIPS32: liveins: $a0 69 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 70 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 71 ; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16) 72 ; MIPS32: $v0 = COPY [[ANYEXT]](s32) 73 ; MIPS32: RetRA implicit $v0 74 %0:_(p0) = COPY $a0 75 %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px) 76 %2:_(s16) = G_ZEXT %1(s8) 77 %3:_(s32) = G_ANYEXT %2(s16) 78 $v0 = COPY %3(s32) 79 RetRA implicit $v0 80 81... 82--- 83name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32 84alignment: 4 85tracksRegLiveness: true 86body: | 87 bb.1.entry: 88 liveins: $a0 89 90 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32 91 ; MIPS32: liveins: $a0 92 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 93 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 94 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32) 95 ; MIPS32: RetRA implicit $v0 96 %0:_(p0) = COPY $a0 97 %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px) 98 %2:_(s16) = G_ZEXT %1(s8) 99 %3:_(s32) = G_ZEXT %2(s16) 100 $v0 = COPY %3(s32) 101 RetRA implicit $v0 102 103... 104--- 105name: load4_s32_to_zextLoad4_s64 106alignment: 4 107tracksRegLiveness: true 108body: | 109 bb.1.entry: 110 liveins: $a0 111 112 ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64 113 ; MIPS32: liveins: $a0 114 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 115 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px) 116 ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64) 117 ; MIPS32: $v0 = COPY [[UV]](s32) 118 ; MIPS32: $v1 = COPY [[UV1]](s32) 119 ; MIPS32: RetRA implicit $v0, implicit $v1 120 %0:_(p0) = COPY $a0 121 %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px) 122 %2:_(s64) = G_ZEXT %1(s32) 123 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) 124 $v0 = COPY %3(s32) 125 $v1 = COPY %4(s32) 126 RetRA implicit $v0, implicit $v1 127 128... 129--- 130name: load1_s8_to_sextLoad1_s32 131alignment: 4 132tracksRegLiveness: true 133body: | 134 bb.1.entry: 135 liveins: $a0 136 137 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32 138 ; MIPS32: liveins: $a0 139 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 140 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 141 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 142 ; MIPS32: RetRA implicit $v0 143 %0:_(p0) = COPY $a0 144 %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px) 145 %2:_(s32) = G_SEXT %1(s8) 146 $v0 = COPY %2(s32) 147 RetRA implicit $v0 148 149... 150--- 151name: load2_s16_to_sextLoad2_s32 152alignment: 4 153tracksRegLiveness: true 154body: | 155 bb.1.entry: 156 liveins: $a0 157 158 ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32 159 ; MIPS32: liveins: $a0 160 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 161 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px) 162 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 163 ; MIPS32: RetRA implicit $v0 164 %0:_(p0) = COPY $a0 165 %1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px) 166 %2:_(s32) = G_SEXT %1(s16) 167 $v0 = COPY %2(s32) 168 RetRA implicit $v0 169 170... 171--- 172name: load1_s8_to_sextLoad1_s16 173alignment: 4 174tracksRegLiveness: true 175body: | 176 bb.1.entry: 177 liveins: $a0 178 179 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16 180 ; MIPS32: liveins: $a0 181 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 182 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 183 ; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16) 184 ; MIPS32: $v0 = COPY [[ANYEXT]](s32) 185 ; MIPS32: RetRA implicit $v0 186 %0:_(p0) = COPY $a0 187 %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px) 188 %2:_(s16) = G_SEXT %1(s8) 189 %3:_(s32) = G_ANYEXT %2(s16) 190 $v0 = COPY %3(s32) 191 RetRA implicit $v0 192 193... 194--- 195name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32 196alignment: 4 197tracksRegLiveness: true 198body: | 199 bb.1.entry: 200 liveins: $a0 201 202 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32 203 ; MIPS32: liveins: $a0 204 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 205 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px) 206 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) 207 ; MIPS32: RetRA implicit $v0 208 %0:_(p0) = COPY $a0 209 %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px) 210 %2:_(s16) = G_SEXT %1(s8) 211 %3:_(s32) = G_SEXT %2(s16) 212 $v0 = COPY %3(s32) 213 RetRA implicit $v0 214 215... 216--- 217name: load4_s32_to_sextLoad4_s64 218alignment: 4 219tracksRegLiveness: true 220body: | 221 bb.1.entry: 222 liveins: $a0 223 224 ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64 225 ; MIPS32: liveins: $a0 226 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 227 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px) 228 ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64) 229 ; MIPS32: $v0 = COPY [[UV]](s32) 230 ; MIPS32: $v1 = COPY [[UV1]](s32) 231 ; MIPS32: RetRA implicit $v0, implicit $v1 232 %0:_(p0) = COPY $a0 233 %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px) 234 %2:_(s64) = G_SEXT %1(s32) 235 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) 236 $v0 = COPY %3(s32) 237 $v1 = COPY %4(s32) 238 RetRA implicit $v0, implicit $v1 239 240... 241