1; RUN: llc -march=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \ 2; RUN: --check-prefixes=ASM,ALL 3; RUN: llc -march=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \ 4; RUN: llvm-objdump -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL 5 6; Test that spill and reloads use the dsp "variant" instructions. We use -O0 7; to use the simple register allocator. 8 9; To test the micromips output, we have to take a round trip through the 10; object file encoder/decoder as the instruction mapping tables are used to 11; support micromips. 12 13; FIXME: We should be able to get rid of those instructions with the variable 14; value registers. 15 16; ALL-LABEL: spill_reload{{>?}}: 17 18define <4 x i8> @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) { 19entry: 20 %c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b) 21 %cond = icmp eq i32 %g, 0 22 br i1 %cond, label %true, label %end 23 24; ASM: SWDSP 25; ASM: SWDSP 26 27; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp) 28; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp) 29 30true: 31 ret <4 x i8> %c 32 33; ASM: LWDSP 34 35; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp) 36 37end: 38 %d = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %c, <4 x i8> %a) 39 ret <4 x i8> %d 40 41; ASM: LWDSP 42; ASM: LWDSP 43 44; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp) 45; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp) 46 47} 48 49declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind 50