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1; RUN: llc -mtriple=mipsel-- -disable-mips-delay-filler \
2; RUN:     -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC32
3; RUN: llc -mtriple=mips64el-- -disable-mips-delay-filler \
4; RUN:     -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC64
5
6; RUN: llc -mtriple=mipsel-- -mattr=+micromips -disable-mips-delay-filler \
7; RUN:     -relocation-model=pic < %s | FileCheck %s -check-prefix=MM
8
9; RUN: llc -mtriple=mipsel-- -disable-mips-delay-filler \
10; RUN:     -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC32
11; RUN: llc -mtriple=mips64el-- -disable-mips-delay-filler \
12; RUN:     -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC64
13
14; RUN: llc -mtriple=mipsel-- -disable-mips-delay-filler -mips-fix-global-base-reg=false \
15; RUN:     -relocation-model=static < %s | FileCheck %s -check-prefix=STATICGP32
16; RUN: llc -mtriple=mips64el-- -disable-mips-delay-filler -mips-fix-global-base-reg=false \
17; RUN:     -relocation-model=static < %s | FileCheck %s -check-prefix=STATICGP64
18
19@t1 = thread_local global i32 0, align 4
20
21define i32 @f1() nounwind {
22entry:
23  %tmp = load i32, i32* @t1, align 4
24  ret i32 %tmp
25
26; PIC32-LABEL:       f1:
27; PIC32-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
28; PIC32-DAG:   addiu   $4, $[[R0]], %tlsgd(t1)
29; PIC32-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
30; PIC32-DAG:   jalr    $25
31; PIC32-DAG:   lw      $2, 0($2)
32
33; PIC64-LABEL:       f1:
34; PIC64-DAG:   daddiu  $[[R0:[a-z0-9]+]], $1, %lo(%neg(%gp_rel(f1)))
35; PIC64-DAG:   daddiu  $4, $[[R0]], %tlsgd(t1)
36; PIC64-DAG:   ld      $25, %call16(__tls_get_addr)($[[R0]])
37; PIC64-DAG:   jalr    $25
38; PIC64-DAG:   lw      $2, 0($2)
39
40; MM-LABEL:       f1:
41; MM-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
42; MM-DAG:   addiu   $4, $[[R0]], %tlsgd(t1)
43; MM-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
44; MM-DAG:   move    $gp, $2
45; MM-DAG:   jalr    $25
46; MM-DAG:   lw16    $2, 0($2)
47
48; STATIC32-LABEL:   f1:
49; STATIC32:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
50; STATIC32:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
51; STATIC32:   rdhwr   $3, $29{{$}}
52; STATIC32:   addu    $[[R2:[0-9]+]], $3, $[[R1]]
53; STATIC32:   lw      $2, 0($[[R2]])
54
55; STATIC64-LABEL:   f1:
56; STATIC64:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
57; STATIC64:   daddiu  $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
58; STATIC64:   rdhwr   $3, $29{{$}}
59; STATIC64:   daddu   $[[R2:[0-9]+]], $3, $[[R0]]
60; STATIC64:   lw      $2, 0($[[R2]])
61}
62
63@t2 = external thread_local global i32
64
65define i32 @f2() nounwind {
66entry:
67  %tmp = load i32, i32* @t2, align 4
68  ret i32 %tmp
69
70; PIC32-LABEL:       f2:
71; PIC32-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
72; PIC32-DAG:   addiu   $4, $[[R0]], %tlsgd(t2)
73; PIC32-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
74; PIC32-DAG:   jalr    $25
75; PIC32-DAG:   lw      $2, 0($2)
76
77; PIC64-LABEL:       f2:
78; PIC64-DAG:   daddiu  $[[R0:[a-z0-9]+]], $1, %lo(%neg(%gp_rel(f2)))
79; PIC64-DAG:   daddiu  $4, $[[R0]], %tlsgd(t2)
80; PIC64-DAG:   ld      $25, %call16(__tls_get_addr)($[[R0]])
81; PIC64-DAG:   jalr    $25
82; PIC64-DAG:   lw      $2, 0($2)
83
84; MM-LABEL:       f2:
85; MM-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
86; MM-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
87; MM-DAG:   addiu   $4, $[[R0]], %tlsgd(t2)
88; MM-DAG:   jalr    $25
89; MM-DAG:   lw16    $2, 0($2)
90
91; STATICGP32-LABEL: f2:
92; STATICGP32: lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
93; STATICGP32: addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
94; STATICGP32: lw      ${{[0-9]+}}, %gottprel(t2)($[[GP]])
95
96; STATICGP64-LABEL: f2:
97; STATICGP64: lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
98; STATICGP64: daddiu  $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
99; STATICGP64: ld      $1, %gottprel(t2)($[[GP]])
100
101; STATIC32-LABEL:   f2:
102; STATIC32:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
103; STATIC32:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
104; STATIC32:   rdhwr   $3, $29{{$}}
105; STATIC32:   lw      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
106; STATIC32:   addu    $[[R1:[0-9]+]], $3, $[[R0]]
107; STATIC32:   lw      $2, 0($[[R1]])
108
109; STATIC64-LABEL:   f2:
110; STATIC64:   lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
111; STATIC64:   daddiu  $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
112; STATIC64:   rdhwr   $3, $29{{$}}
113; STATIC64:   ld      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
114; STATIC64:   daddu   $[[R1:[0-9]+]], $3, $[[R0]]
115; STATIC64:   lw      $2, 0($[[R1]])
116}
117
118@f3.i = internal thread_local unnamed_addr global i32 1, align 4
119
120define i32 @f3() nounwind {
121entry:
122; PIC32-LABEL:      f3:
123; PIC32:   addu    $[[R0:[a-z0-9]+]], $2, $25
124; PIC32:   addiu   $4, $[[R0]], %tlsldm(f3.i)
125; PIC32:   lw      $25, %call16(__tls_get_addr)($[[R0]])
126; PIC32:   jalr    $25
127; PIC32:   lui     $[[R0:[0-9]+]], %dtprel_hi(f3.i)
128; PIC32:   addu    $[[R1:[0-9]+]], $[[R0]], $2
129; PIC32:   lw      $[[R3:[0-9]+]], %dtprel_lo(f3.i)($[[R1]])
130; PIC32:   addiu   $[[R3]], $[[R3]], 1
131; PIC32:   sw      $[[R3]], %dtprel_lo(f3.i)($[[R1]])
132
133; PIC64-LABEL:      f3:
134; PIC64:   lui     $[[R0:[a-z0-9]+]], %hi(%neg(%gp_rel(f3)))
135; PIC64:   daddu   $[[R0]], $[[R0]], $25
136; PIC64:   daddiu  $[[R1:[a-z0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f3)))
137; PIC64:   daddiu  $4, $[[R1]], %tlsldm(f3.i)
138; PIC64:   ld      $25, %call16(__tls_get_addr)($[[R1]])
139; PIC64:   jalr    $25
140; PIC64:   lui     $[[R0:[0-9]+]], %dtprel_hi(f3.i)
141; PIC64:   daddu   $[[R1:[0-9]+]], $[[R0]], $2
142; PIC64:   lw      $[[R2:[0-9]+]], %dtprel_lo(f3.i)($[[R1]])
143; PIC64:   addiu   $[[R2]], $[[R2]], 1
144; PIC64:   sw      $[[R2]], %dtprel_lo(f3.i)($[[R1]])
145
146; MM-LABEL:       f3:
147; MM:   addiu   $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
148; MM:   jalr    $25
149; MM:   lui     $[[R0:[0-9]+]], %dtprel_hi(f3.i)
150; MM:   addu16  $[[R1:[0-9]+]], $[[R0]], $2
151; MM:   lw      ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]])
152
153  %0 = load i32, i32* @f3.i, align 4
154  %inc = add nsw i32 %0, 1
155  store i32 %inc, i32* @f3.i, align 4
156  ret i32 %inc
157}
158