1; RUN: llc -ppc-gpr-icmps=all -mtriple=powerpc64-unknown-linux-gnu \ 2; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s 3; RUN: llc -ppc-gpr-icmps=all -mtriple=powerpc64-unknown-linux-gnu \ 4; RUN: -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | \ 5; RUN: FileCheck --check-prefix=CHECK-NO-ISEL %s 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 7; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 -ppc-gpr-icmps=none < %s | \ 8; RUN: FileCheck %s --check-prefix=CHECK-P10 9; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 10; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 -ppc-gpr-icmps=none < %s | \ 11; RUN: FileCheck %s --check-prefix=CHECK-P10 12 13; Function Attrs: nounwind readnone 14define zeroext i1 @test1(float %v1, float %v2) #0 { 15entry: 16 %cmp = fcmp oge float %v1, %v2 17 %cmp2 = fcmp ole float %v2, 0.000000e+00 18 %and5 = and i1 %cmp, %cmp2 19 ret i1 %and5 20 21; CHECK-LABEL: @test1 22; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 23; CHECK-DAG: li [[REG1:[0-9]+]], 1 24; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]] 25; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 26; CHECK: crnor 27; CHECK: crnor 28; CHECK: crnand [[REG4:[0-9]+]], 29; CHECK: isel 3, 0, [[REG1]], [[REG4]] 30; CHECK-NO-ISEL-LABEL: @test1 31; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 32; CHECK-NO-ISEL-NEXT: blr 33; CHECK-NO-ISEL-NEXT: [[TRUE]] 34; CHECK-NO-ISEL-NEXT: li 3, 0 35; CHECK-NO-ISEL-NEXT: blr 36; CHECK: blr 37 38; CHECK-P10-LABEL: test1: 39; CHECK-P10: # %bb.0: # %entry 40; CHECK-P10-NEXT: fcmpu cr0, f1, f2 41; CHECK-P10-NEXT: xxlxor f0, f0, f0 42; CHECK-P10-NEXT: fcmpu cr1, f2, f2 43; CHECK-P10-NEXT: crnor 4*cr5+lt, un, lt 44; CHECK-P10-NEXT: fcmpu cr0, f2, f0 45; CHECK-P10-NEXT: crnor 4*cr5+gt, 4*cr1+un, gt 46; CHECK-P10-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt 47; CHECK-P10-NEXT: setbc r3, 4*cr5+lt 48; CHECK-P10-NEXT: blr 49} 50 51; Function Attrs: nounwind readnone 52define zeroext i1 @test2(float %v1, float %v2) #0 { 53entry: 54 %cmp = fcmp oge float %v1, %v2 55 %cmp2 = fcmp ole float %v2, 0.000000e+00 56 %xor5 = xor i1 %cmp, %cmp2 57 ret i1 %xor5 58 59; CHECK-LABEL: @test2 60; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 61; CHECK-DAG: li [[REG1:[0-9]+]], 1 62; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]] 63; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 64; CHECK: crnor 65; CHECK: crnor 66; CHECK: creqv [[REG4:[0-9]+]], 67; CHECK: isel 3, 0, [[REG1]], [[REG4]] 68; CHECK: blr 69 70; CHECK-P10-LABEL: test2: 71; CHECK-P10: # %bb.0: # %entry 72; CHECK-P10-NEXT: fcmpu cr0, f1, f2 73; CHECK-P10-NEXT: xxlxor f0, f0, f0 74; CHECK-P10-NEXT: fcmpu cr1, f2, f2 75; CHECK-P10-NEXT: crnor 4*cr5+lt, un, lt 76; CHECK-P10-NEXT: fcmpu cr0, f2, f0 77; CHECK-P10-NEXT: crnor 4*cr5+gt, 4*cr1+un, gt 78; CHECK-P10-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt 79; CHECK-P10-NEXT: setbc r3, 4*cr5+lt 80; CHECK-P10-NEXT: blr 81} 82 83; Function Attrs: nounwind readnone 84define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 { 85entry: 86 %cmp = fcmp oge float %v1, %v2 87 %cmp2 = fcmp ole float %v2, 0.000000e+00 88 %cmp4 = icmp ne i32 %x, -2 89 %and7 = and i1 %cmp2, %cmp4 90 %xor8 = xor i1 %cmp, %and7 91 ret i1 %xor8 92 93; CHECK-LABEL: @test3 94; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 95; CHECK-DAG: li [[REG1:[0-9]+]], 1 96; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]] 97; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 98; CHECK: crnor 99; CHECK: crnor 100; CHECK: crandc 101; CHECK: creqv [[REG4:[0-9]+]], 102; CHECK: isel 3, 0, [[REG1]], [[REG4]] 103; CHECK: blr 104 105; CHECK-P10-LABEL: test3: 106; CHECK-P10: # %bb.0: # %entry 107; CHECK-P10-NEXT: fcmpu cr0, f1, f2 108; CHECK-P10-NEXT: xxlxor f0, f0, f0 109; CHECK-P10-NEXT: fcmpu cr1, f2, f2 110; CHECK-P10-NEXT: crnor 4*cr5+lt, un, lt 111; CHECK-P10-NEXT: fcmpu cr0, f2, f0 112; CHECK-P10-NEXT: crnor 4*cr5+gt, 4*cr1+un, gt 113; CHECK-P10-NEXT: cmpwi r5, -2 114; CHECK-P10-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq 115; CHECK-P10-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt 116; CHECK-P10-NEXT: setbc r3, 4*cr5+lt 117; CHECK-P10-NEXT: blr 118} 119 120; Function Attrs: nounwind readnone 121define zeroext i1 @test4(i1 zeroext %v1, i1 zeroext %v2, i1 zeroext %v3) #0 { 122entry: 123 %and8 = and i1 %v1, %v2 124 %or9 = or i1 %and8, %v3 125 ret i1 %or9 126 127; CHECK-DAG: @test4 128; CHECK: and [[REG1:[0-9]+]], 3, 4 129; CHECK: or 3, [[REG1]], 5 130; CHECK: blr 131} 132 133; Function Attrs: nounwind readnone 134define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 { 135entry: 136 %and6 = and i1 %v1, %v2 137 %cmp = icmp ne i32 %v3, -2 138 %or7 = or i1 %and6, %cmp 139 ret i1 %or7 140 141; CHECK-LABEL: @test5 142; CHECK-DAG: li [[NEG2:[0-9]+]], -2 143; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4 144; CHECK-DAG: xor [[NE1:[0-9]+]], 5, [[NEG2]] 145; CHECK-DAG: clrldi [[TRUNC:[0-9]+]], [[REG1]], 63 146; CHECK-DAG: cntlzw [[NE2:[0-9]+]], [[NE1]] 147; CHECK: srwi [[NE3:[0-9]+]], [[NE2]], 5 148; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1 149; CHECK: or 3, [[TRUNC]], [[NE4]] 150; CHECK-NEXT: blr 151 152; CHECK-P10-LABEL: test5: 153; CHECK-P10: # %bb.0: # %entry 154; CHECK-P10-NEXT: and r3, r3, r4 155; CHECK-P10-NEXT: cmpwi cr1, r5, -2 156; CHECK-P10-NEXT: andi. r3, r3, 1 157; CHECK-P10-NEXT: crorc 4*cr5+lt, gt, 4*cr1+eq 158; CHECK-P10-NEXT: setbc r3, 4*cr5+lt 159; CHECK-P10-NEXT: blr 160} 161 162; Function Attrs: nounwind readnone 163define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 { 164entry: 165 %cmp = icmp ne i32 %v3, -2 166 %or6 = or i1 %cmp, %v2 167 %and7 = and i1 %or6, %v1 168 ret i1 %and7 169 170; CHECK-LABEL: @test6 171; CHECK-DAG: li [[NEG2:[0-9]+]], -2 172; CHECK-DAG: clrldi [[CLR1:[0-9]+]], 4, 63 173; CHECK-DAG: clrldi [[CLR2:[0-9]+]], 3, 63 174; CHECK-DAG: xor [[NE1:[0-9]+]], 5, [[NEG2]] 175; CHECK-DAG: cntlzw [[NE2:[0-9]+]], [[NE1]] 176; CHECK: srwi [[NE3:[0-9]+]], [[NE2]], 5 177; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1 178; CHECK: or [[OR:[0-9]+]], [[NE4]], [[CLR1]] 179; CHECK: and 3, [[OR]], [[CLR2]] 180; CHECK-NEXT: blr 181 182; CHECK-P10-LABEL: test6: 183; CHECK-P10: # %bb.0: # %entry 184; CHECK-P10-NEXT: andi. r3, r3, 1 185; CHECK-P10-NEXT: cmpwi cr1, r5, -2 186; CHECK-P10-NEXT: crmove 4*cr5+lt, gt 187; CHECK-P10-NEXT: andi. r3, r4, 1 188; CHECK-P10-NEXT: crorc 4*cr5+gt, gt, 4*cr1+eq 189; CHECK-P10-NEXT: crand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt 190; CHECK-P10-NEXT: setbc r3, 4*cr5+lt 191; CHECK-P10-NEXT: blr 192} 193 194; Function Attrs: nounwind readnone 195define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 { 196entry: 197 %cond = select i1 %v2, i32 %i1, i32 %i2 198 ret i32 %cond 199 200; CHECK-LABEL: @test7 201; CHECK: andi. {{[0-9]+}}, 3, 1 202; CHECK: iselgt 3, 4, 5 203; CHECK: blr 204} 205 206define signext i32 @exttest7(i32 signext %a) #0 { 207entry: 208 %cmp = icmp eq i32 %a, 5 209 %cond = select i1 %cmp, i32 7, i32 8 210 ret i32 %cond 211 212; CHECK-LABEL: @exttest7 213; CHECK-DAG: cmpwi 3, 5 214; CHECK-DAG: li [[REG1:[0-9]+]], 8 215; CHECK-DAG: li [[REG2:[0-9]+]], 7 216; CHECK: iseleq 3, [[REG2]], [[REG1]] 217; CHECK-NOT: rldicl 218; CHECK: blr 219} 220 221define zeroext i32 @exttest8() #0 { 222entry: 223 %v0 = load i64, i64* undef, align 8 224 %sub = sub i64 80, %v0 225 %div = lshr i64 %sub, 1 226 %conv13 = trunc i64 %div to i32 227 %cmp14 = icmp ugt i32 %conv13, 80 228 %.conv13 = select i1 %cmp14, i32 0, i32 %conv13 229 ret i32 %.conv13 230; CHECK-LABEL: @exttest8 231; This is a don't-crash test: %conv13 is both one of the possible select output 232; values and also an input to the conditional feeding it. 233} 234 235; Function Attrs: nounwind readnone 236define float @test8(i1 zeroext %v2, float %v1, float %v3) #0 { 237entry: 238 %cond = select i1 %v2, float %v1, float %v3 239 ret float %cond 240 241; CHECK-LABEL: @test8 242; CHECK: andi. {{[0-9]+}}, 3, 1 243; CHECK: bclr 12, 1, 0 244; CHECK: fmr 1, 2 245; CHECK: blr 246} 247 248; Function Attrs: nounwind readnone 249define signext i32 @test10(i32 signext %v1, i32 signext %v2) #0 { 250entry: 251 %tobool = icmp ne i32 %v1, 0 252 %lnot = icmp eq i32 %v2, 0 253 %and3 = and i1 %tobool, %lnot 254 %and = zext i1 %and3 to i32 255 ret i32 %and 256 257; CHECK-LABEL: @test10 258; CHECK-DAG: cntlzw 3, 3 259; CHECK-DAG: cntlzw 4, 4 260; CHECK-DAG: srwi 3, 3, 5 261; CHECK-DAG: srwi 4, 4, 5 262; CHECK: xori 3, 3, 1 263; CHECK: and 3, 3, 4 264; CHECK-NEXT: blr 265 266; CHECK-P10-LABEL: test10: 267; CHECK-P10: # %bb.0: # %entry 268; CHECK-P10-NEXT: cmpwi r3, 0 269; CHECK-P10-NEXT: cmpwi cr1, r4, 0 270; CHECK-P10-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq 271; CHECK-P10-NEXT: setbc r3, 4*cr5+lt 272; CHECK-P10-NEXT: blr 273} 274 275attributes #0 = { nounwind readnone } 276 277