1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ 3; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s 4 5define float @absf(float %a) { 6; CHECK-LABEL: absf: 7; CHECK: # %bb.0: # %entry 8; CHECK-NEXT: xsabsdp f1, f1 9; CHECK-NEXT: blr 10entry: 11 %conv = bitcast float %a to i32 12 %and = and i32 %conv, 2147483647 13 %conv1 = bitcast i32 %and to float 14 ret float %conv1 15} 16 17define double @absd(double %a) { 18; CHECK-LABEL: absd: 19; CHECK: # %bb.0: # %entry 20; CHECK-NEXT: xsabsdp f1, f1 21; CHECK-NEXT: blr 22entry: 23 %conv = bitcast double %a to i64 24 %and = and i64 %conv, 9223372036854775807 25 %conv1 = bitcast i64 %and to double 26 ret double %conv1 27} 28 29define <4 x float> @absv4f32(<4 x float> %a) { 30; CHECK-LABEL: absv4f32: 31; CHECK: # %bb.0: # %entry 32; CHECK-NEXT: xvabssp vs34, vs34 33; CHECK-NEXT: blr 34entry: 35 %conv = bitcast <4 x float> %a to <4 x i32> 36 %and = and <4 x i32> %conv, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 37 %conv1 = bitcast <4 x i32> %and to <4 x float> 38 ret <4 x float> %conv1 39} 40 41define <4 x float> @absv4f32_wundef(<4 x float> %a) { 42; CHECK-LABEL: absv4f32_wundef: 43; CHECK: # %bb.0: # %entry 44; CHECK-NEXT: xvabssp vs34, vs34 45; CHECK-NEXT: blr 46entry: 47 %conv = bitcast <4 x float> %a to <4 x i32> 48 %and = and <4 x i32> %conv, <i32 2147483647, i32 undef, i32 undef, i32 2147483647> 49 %conv1 = bitcast <4 x i32> %and to <4 x float> 50 ret <4 x float> %conv1 51} 52 53define <4 x float> @absv4f32_invalid(<4 x float> %a) { 54; CHECK-LABEL: absv4f32_invalid: 55; CHECK: # %bb.0: # %entry 56; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha 57; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l 58; CHECK-NEXT: lvx v3, 0, r3 59; CHECK-NEXT: xxland vs34, vs34, vs35 60; CHECK-NEXT: blr 61entry: 62 %conv = bitcast <4 x float> %a to <4 x i32> 63 %and = and <4 x i32> %conv, <i32 2147483646, i32 2147483647, i32 2147483647, i32 2147483647> 64 %conv1 = bitcast <4 x i32> %and to <4 x float> 65 ret <4 x float> %conv1 66} 67 68define <2 x double> @absv2f64(<2 x double> %a) { 69; CHECK-LABEL: absv2f64: 70; CHECK: # %bb.0: # %entry 71; CHECK-NEXT: xvabsdp vs34, vs34 72; CHECK-NEXT: blr 73entry: 74 %conv = bitcast <2 x double> %a to <2 x i64> 75 %and = and <2 x i64> %conv, <i64 9223372036854775807, i64 9223372036854775807> 76 %conv1 = bitcast <2 x i64> %and to <2 x double> 77 ret <2 x double> %conv1 78} 79 80define float @negf(float %a) { 81; CHECK-LABEL: negf: 82; CHECK: # %bb.0: # %entry 83; CHECK-NEXT: xsnegdp f1, f1 84; CHECK-NEXT: blr 85entry: 86 %conv = bitcast float %a to i32 87 %and = xor i32 %conv, -2147483648 88 %conv1 = bitcast i32 %and to float 89 ret float %conv1 90} 91 92define double @negd(double %a) { 93; CHECK-LABEL: negd: 94; CHECK: # %bb.0: # %entry 95; CHECK-NEXT: xsnegdp f1, f1 96; CHECK-NEXT: blr 97entry: 98 %conv = bitcast double %a to i64 99 %and = xor i64 %conv, -9223372036854775808 100 %conv1 = bitcast i64 %and to double 101 ret double %conv1 102} 103 104define <4 x float> @negv4f32(<4 x float> %a) { 105; CHECK-LABEL: negv4f32: 106; CHECK: # %bb.0: # %entry 107; CHECK-NEXT: xvnegsp vs34, vs34 108; CHECK-NEXT: blr 109entry: 110 %conv = bitcast <4 x float> %a to <4 x i32> 111 %and = xor <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 112 %conv1 = bitcast <4 x i32> %and to <4 x float> 113 ret <4 x float> %conv1 114} 115 116define <2 x double> @negv2d64(<2 x double> %a) { 117; CHECK-LABEL: negv2d64: 118; CHECK: # %bb.0: # %entry 119; CHECK-NEXT: xvnegdp vs34, vs34 120; CHECK-NEXT: blr 121entry: 122 %conv = bitcast <2 x double> %a to <2 x i64> 123 %and = xor <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808> 124 %conv1 = bitcast <2 x i64> %and to <2 x double> 125 ret <2 x double> %conv1 126} 127define float @nabsf(float %a) { 128; CHECK-LABEL: nabsf: 129; CHECK: # %bb.0: # %entry 130; CHECK-NEXT: xsnabsdp f1, f1 131; CHECK-NEXT: blr 132entry: 133 %conv = bitcast float %a to i32 134 %and = or i32 %conv, -2147483648 135 %conv1 = bitcast i32 %and to float 136 ret float %conv1 137} 138 139define double @nabsd(double %a) { 140; CHECK-LABEL: nabsd: 141; CHECK: # %bb.0: # %entry 142; CHECK-NEXT: xsnabsdp f1, f1 143; CHECK-NEXT: blr 144entry: 145 %conv = bitcast double %a to i64 146 %and = or i64 %conv, -9223372036854775808 147 %conv1 = bitcast i64 %and to double 148 ret double %conv1 149} 150 151define <4 x float> @nabsv4f32(<4 x float> %a) { 152; CHECK-LABEL: nabsv4f32: 153; CHECK: # %bb.0: # %entry 154; CHECK-NEXT: xvnabssp vs34, vs34 155; CHECK-NEXT: blr 156entry: 157 %conv = bitcast <4 x float> %a to <4 x i32> 158 %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 159 %conv1 = bitcast <4 x i32> %and to <4 x float> 160 ret <4 x float> %conv1 161} 162 163define <2 x double> @nabsv2d64(<2 x double> %a) { 164; CHECK-LABEL: nabsv2d64: 165; CHECK: # %bb.0: # %entry 166; CHECK-NEXT: xvnabsdp vs34, vs34 167; CHECK-NEXT: blr 168entry: 169 %conv = bitcast <2 x double> %a to <2 x i64> 170 %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808> 171 %conv1 = bitcast <2 x i64> %and to <2 x double> 172 ret <2 x double> %conv1 173} 174 175