1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=BE 3;RUN: llc < %s --mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=LE 4 5define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) { 6; BE-LABEL: test_large_vec_vaarg: 7; BE: # %bb.0: 8; BE-NEXT: ld 3, -8(1) 9; BE-NEXT: addi 3, 3, 15 10; BE-NEXT: rldicr 3, 3, 0, 59 11; BE-NEXT: addi 4, 3, 16 12; BE-NEXT: addi 5, 3, 31 13; BE-NEXT: std 4, -8(1) 14; BE-NEXT: rldicr 4, 5, 0, 59 15; BE-NEXT: lvx 2, 0, 3 16; BE-NEXT: addi 3, 4, 16 17; BE-NEXT: std 3, -8(1) 18; BE-NEXT: lvx 3, 0, 4 19; BE-NEXT: blr 20; 21; LE-LABEL: test_large_vec_vaarg: 22; LE: # %bb.0: 23; LE-NEXT: ld 3, -8(1) 24; LE-NEXT: addi 3, 3, 15 25; LE-NEXT: rldicr 3, 3, 0, 59 26; LE-NEXT: addi 4, 3, 31 27; LE-NEXT: addi 5, 3, 16 28; LE-NEXT: rldicr 4, 4, 0, 59 29; LE-NEXT: std 5, -8(1) 30; LE-NEXT: addi 5, 4, 16 31; LE-NEXT: lvx 2, 0, 3 32; LE-NEXT: std 5, -8(1) 33; LE-NEXT: lvx 3, 0, 4 34; LE-NEXT: blr 35 %args = alloca i8*, align 4 36 %x = va_arg i8** %args, <8 x i32> 37 ret <8 x i32> %x 38} 39