1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P9 3; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P8 4 5define signext i64 @maddld64(i64 signext %a, i64 signext %b) { 6; CHECK-LABEL: maddld64: 7; CHECK: # %bb.0: # %entry 8; CHECK-P9-NEXT: maddld 3, 4, 3, 3 9; CHECK-P8-NEXT: mulld 4, 4, 3 10; CHECK-P8-NEXT: add 3, 4, 3 11; CHECK-NEXT: blr 12 13entry: 14 %mul = mul i64 %b, %a 15 %add = add i64 %mul, %a 16 ret i64 %add 17} 18 19define signext i32 @maddld32(i32 signext %a, i32 signext %b) { 20; CHECK-LABEL: maddld32: 21; CHECK: # %bb.0: # %entry 22; CHECK-P9-NEXT: maddld 3, 4, 3, 3 23; CHECK-P9-NEXT: extsw 3, 3 24; CHECK-P8-NEXT: mullw 4, 4, 3 25; CHECK-P8-NEXT: add 3, 4, 3 26; CHECK-P8-NEXT: extsw 3, 3 27; CHECK-NEXT: blr 28 29entry: 30 %mul = mul i32 %b, %a 31 %add = add i32 %mul, %a 32 ret i32 %add 33} 34 35define signext i16 @maddld16(i16 signext %a, i16 signext %b, i16 signext %c) { 36; CHECK-LABEL: maddld16: 37; CHECK: # %bb.0: # %entry 38; CHECK-P9-NEXT: maddld 3, 4, 3, 5 39; CHECK-P9-NEXT: extsh 3, 3 40; CHECK-P8-NEXT: mullw 3, 4, 3 41; CHECK-P8-NEXT: add 3, 3, 5 42; CHECK-P8-NEXT: extsh 3, 3 43; CHECK-NEXT: blr 44 45entry: 46 %mul = mul i16 %b, %a 47 %add = add i16 %mul, %c 48 ret i16 %add 49} 50 51define zeroext i32 @maddld32zeroext(i32 zeroext %a, i32 zeroext %b) { 52; CHECK-LABEL: maddld32zeroext: 53; CHECK: # %bb.0: # %entry 54; CHECK-P9-NEXT: maddld 3, 4, 3, 3 55; CHECK-P8-NEXT: mullw 4, 4, 3 56; CHECK-P8-NEXT: add 3, 4, 3 57; CHECK-NEXT: clrldi 3, 3, 32 58; CHECK-NEXT: blr 59 60entry: 61 %mul = mul i32 %b, %a 62 %add = add i32 %mul, %a 63 ret i32 %add 64} 65 66define signext i32 @maddld32nsw(i32 signext %a, i32 signext %b) { 67; CHECK-LABEL: maddld32nsw: 68; CHECK: # %bb.0: # %entry 69; CHECK-P9-NEXT: maddld 3, 4, 3, 3 70; CHECK-P8-NEXT: mullw 4, 4, 3 71; CHECK-P8-NEXT: add 3, 4, 3 72; CHECK-NEXT: extsw 3, 3 73; CHECK-NEXT: blr 74 75entry: 76 %mul = mul nsw i32 %b, %a 77 %add = add nsw i32 %mul, %a 78 ret i32 %add 79} 80 81define zeroext i32 @maddld32nuw(i32 zeroext %a, i32 zeroext %b) { 82; CHECK-LABEL: maddld32nuw: 83; CHECK: # %bb.0: # %entry 84; CHECK-P9-NEXT: maddld 3, 4, 3, 3 85; CHECK-P8-NEXT: mullw 4, 4, 3 86; CHECK-P8-NEXT: add 3, 4, 3 87; CHECK-NEXT: clrldi 3, 3, 32 88; CHECK-NEXT: blr 89 90entry: 91 %mul = mul nuw i32 %b, %a 92 %add = add nuw i32 %mul, %a 93 ret i32 %add 94} 95 96define signext i64 @maddld64_imm(i64 signext %a, i64 signext %b) { 97; CHECK-LABEL: maddld64_imm: 98; CHECK: # %bb.0: # %entry 99; CHECK-NOT: maddld 100; CHECK-NEXT: mulli 4, 4, 13 101; CHECK-NEXT: add 3, 4, 3 102; CHECK-NEXT: blr 103 104entry: 105 %mul = mul i64 %b, 13 106 %add = add i64 %mul, %a 107 ret i64 %add 108} 109 110define signext i32 @maddld32_imm(i32 signext %a, i32 signext %b) { 111; CHECK-LABEL: maddld32_imm: 112; CHECK: # %bb.0: # %entry 113; CHECK-NOT: maddld 114; CHECK-NEXT: mullw 3, 4, 3 115; CHECK-NEXT: addi 3, 3, 13 116; CHECK-NEXT: extsw 3, 3 117; CHECK-NEXT: blr 118 119entry: 120 %mul = mul i32 %b, %a 121 %add = add i32 %mul, 13 122 ret i32 %add 123} 124 125define signext i16 @maddld16_imm(i16 signext %a, i16 signext %b, i16 signext %c) { 126; CHECK-LABEL: maddld16_imm: 127; CHECK: # %bb.0: # %entry 128; CHECK-NOT: maddld 129; CHECK-NEXT: mulli 3, 4, 13 130; CHECK-NEXT: add 3, 3, 5 131; CHECK-NEXT: extsh 3, 3 132; CHECK-NEXT: blr 133 134entry: 135 %mul = mul i16 %b, 13 136 %add = add i16 %mul, %c 137 ret i16 %add 138} 139 140define zeroext i32 @maddld32zeroext_imm(i32 zeroext %a, i32 zeroext %b) { 141; CHECK-LABEL: maddld32zeroext_imm: 142; CHECK: # %bb.0: # %entry 143; CHECK-NOT: maddld 144; CHECK-NEXT: mullw 3, 4, 3 145; CHECK-NEXT: addi 3, 3, 13 146; CHECK-NEXT: clrldi 3, 3, 32 147; CHECK-NEXT: blr 148 149entry: 150 %mul = mul i32 %b, %a 151 %add = add i32 %mul, 13 152 ret i32 %add 153} 154 155define signext i32 @maddld32nsw_imm(i32 signext %a, i32 signext %b) { 156; CHECK-LABEL: maddld32nsw_imm: 157; CHECK: # %bb.0: # %entry 158; CHECK-NOT: maddld 159; CHECK-NEXT: mulli 4, 4, 13 160; CHECK-NEXT: add 3, 4, 3 161; CHECK-NEXT: extsw 3, 3 162; CHECK-NEXT: blr 163 164entry: 165 %mul = mul nsw i32 %b, 13 166 %add = add nsw i32 %mul, %a 167 ret i32 %add 168} 169 170define zeroext i32 @maddld32nuw_imm(i32 zeroext %a, i32 zeroext %b) { 171; CHECK-LABEL: maddld32nuw_imm: 172; CHECK: # %bb.0: # %entry 173; CHECK-NOT: maddld 174; CHECK-NEXT: mullw 3, 4, 3 175; CHECK-NEXT: addi 3, 3, 13 176; CHECK-NEXT: clrldi 3, 3, 32 177; CHECK-NEXT: blr 178 179entry: 180 %mul = mul nuw i32 %b, %a 181 %add = add nuw i32 %mul, 13 182 ret i32 %add 183} 184 185define zeroext i32 @maddld32nuw_imm_imm(i32 zeroext %b) { 186; CHECK-LABEL: maddld32nuw_imm_imm: 187; CHECK: # %bb.0: # %entry 188; CHECK-NOT: maddld 189; CHECK-NEXT: mulli 3, 3, 18 190; CHECK-NEXT: addi 3, 3, 13 191; CHECK-NEXT: clrldi 3, 3, 32 192; CHECK-NEXT: blr 193 194entry: 195 %mul = mul nuw i32 %b, 18 196 %add = add nuw i32 %mul, 13 197 ret i32 %add 198} 199 200define zeroext i32 @maddld32nuw_bigimm_imm(i32 zeroext %b) { 201; CHECK-LABEL: maddld32nuw_bigimm_imm: 202; CHECK: # %bb.0: # %entry 203; CHECK-NOT: maddld 204; CHECK-NEXT: lis 4, 26127 205; CHECK-NEXT: ori 4, 4, 63251 206; CHECK-NEXT: mullw 3, 3, 4 207; CHECK-NEXT: addi 3, 3, 13 208; CHECK-NEXT: clrldi 3, 3, 32 209; CHECK-NEXT: blr 210 211entry: 212 %mul = mul nuw i32 %b, 1712322323 213 %add = add nuw i32 %mul, 13 214 ret i32 %add 215} 216 217define zeroext i32 @maddld32nuw_bigimm_bigimm(i32 zeroext %b) { 218; CHECK-LABEL: maddld32nuw_bigimm_bigimm: 219; CHECK: # %bb.0: # %entry 220; CHECK-P9-NEXT: lis 4, -865 221; CHECK-P9-NEXT: lis 5, 26127 222; CHECK-P9-NEXT: ori 4, 4, 42779 223; CHECK-P9-NEXT: ori 5, 5, 63251 224; CHECK-P9-NEXT: maddld 3, 3, 5, 4 225 226; CHECK-P8-NEXT: lis 4, 26127 227; CHECK-P8-NEXT: ori 4, 4, 63251 228; CHECK-P8-NEXT: mullw 3, 3, 4 229; CHECK-P8-NEXT: addi 3, 3, -22757 230; CHECK-P8-NEXT: addis 3, 3, -864 231 232; CHECK-NEXT: clrldi 3, 3, 32 233; CHECK-NEXT: blr 234 235entry: 236 %mul = mul nuw i32 %b, 1712322323 237 %add = add nuw i32 %mul, 17123223323 238 ret i32 %add 239} 240