1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ 4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ 7; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE 8 9; Function Attrs: nofree nounwind writeonly 10define dso_local void @test1(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { 11; CHECK-LABEL: test1: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: xvi16ger2 acc0, v2, v2 14; CHECK-NEXT: xxmfacc acc0 15; CHECK-NEXT: stxv vs0, 48(r7) 16; CHECK-NEXT: stxv vs1, 32(r7) 17; CHECK-NEXT: stxv vs2, 16(r7) 18; CHECK-NEXT: stxv vs3, 0(r7) 19; CHECK-NEXT: blr 20; 21; CHECK-BE-LABEL: test1: 22; CHECK-BE: # %bb.0: # %entry 23; CHECK-BE-NEXT: xvi16ger2 acc0, v2, v2 24; CHECK-BE-NEXT: xxmfacc acc0 25; CHECK-BE-NEXT: stxv vs1, 16(r7) 26; CHECK-BE-NEXT: stxv vs0, 0(r7) 27; CHECK-BE-NEXT: stxv vs3, 48(r7) 28; CHECK-BE-NEXT: stxv vs2, 32(r7) 29; CHECK-BE-NEXT: blr 30entry: 31 %0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> %vc, <16 x i8> %vc) 32 %1 = bitcast i8* %resp to <512 x i1>* 33 store <512 x i1> %0, <512 x i1>* %1, align 64 34 ret void 35} 36 37; Function Attrs: nounwind readnone 38declare <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8>, <16 x i8>) 39 40; Function Attrs: nofree nounwind writeonly 41define dso_local void @test2(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { 42; CHECK-LABEL: test2: 43; CHECK: # %bb.0: # %entry 44; CHECK-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0 45; CHECK-NEXT: xxmfacc acc0 46; CHECK-NEXT: stxv vs0, 48(r7) 47; CHECK-NEXT: stxv vs1, 32(r7) 48; CHECK-NEXT: stxv vs2, 16(r7) 49; CHECK-NEXT: stxv vs3, 0(r7) 50; CHECK-NEXT: blr 51; 52; CHECK-BE-LABEL: test2: 53; CHECK-BE: # %bb.0: # %entry 54; CHECK-BE-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0 55; CHECK-BE-NEXT: xxmfacc acc0 56; CHECK-BE-NEXT: stxv vs1, 16(r7) 57; CHECK-BE-NEXT: stxv vs0, 0(r7) 58; CHECK-BE-NEXT: stxv vs3, 48(r7) 59; CHECK-BE-NEXT: stxv vs2, 32(r7) 60; CHECK-BE-NEXT: blr 61entry: 62 %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) 63 %1 = bitcast i8* %resp to <512 x i1>* 64 store <512 x i1> %0, <512 x i1>* %1, align 64 65 ret void 66} 67 68; Function Attrs: nounwind readnone 69declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8>, <16 x i8>, i32, i32, i32) 70 71; Function Attrs: nofree nounwind 72define dso_local void @test3(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { 73; CHECK-LABEL: test3: 74; CHECK: # %bb.0: # %entry 75; CHECK-NEXT: lxv vs1, 32(r3) 76; CHECK-NEXT: lxv vs0, 48(r3) 77; CHECK-NEXT: lxv vs3, 0(r3) 78; CHECK-NEXT: lxv vs2, 16(r3) 79; CHECK-NEXT: xxmtacc acc0 80; CHECK-NEXT: xvi8ger4spp acc0, v2, v2 81; CHECK-NEXT: xxmfacc acc0 82; CHECK-NEXT: stxv vs0, 48(r7) 83; CHECK-NEXT: stxv vs1, 32(r7) 84; CHECK-NEXT: stxv vs2, 16(r7) 85; CHECK-NEXT: stxv vs3, 0(r7) 86; CHECK-NEXT: blr 87; 88; CHECK-BE-LABEL: test3: 89; CHECK-BE: # %bb.0: # %entry 90; CHECK-BE-NEXT: lxv vs1, 16(r3) 91; CHECK-BE-NEXT: lxv vs0, 0(r3) 92; CHECK-BE-NEXT: lxv vs3, 48(r3) 93; CHECK-BE-NEXT: lxv vs2, 32(r3) 94; CHECK-BE-NEXT: xxmtacc acc0 95; CHECK-BE-NEXT: xvi8ger4spp acc0, v2, v2 96; CHECK-BE-NEXT: xxmfacc acc0 97; CHECK-BE-NEXT: stxv vs1, 16(r7) 98; CHECK-BE-NEXT: stxv vs0, 0(r7) 99; CHECK-BE-NEXT: stxv vs3, 48(r7) 100; CHECK-BE-NEXT: stxv vs2, 32(r7) 101; CHECK-BE-NEXT: blr 102entry: 103 %0 = bitcast i8* %vqp to <512 x i1>* 104 %1 = load <512 x i1>, <512 x i1>* %0, align 64 105 %2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) 106 %3 = bitcast i8* %resp to <512 x i1>* 107 store <512 x i1> %2, <512 x i1>* %3, align 64 108 ret void 109} 110 111; Function Attrs: nounwind readnone 112declare <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>) 113 114; Function Attrs: nofree nounwind 115define dso_local void @test4(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { 116; CHECK-LABEL: test4: 117; CHECK: # %bb.0: # %entry 118; CHECK-NEXT: lxv vs1, 32(r3) 119; CHECK-NEXT: lxv vs0, 48(r3) 120; CHECK-NEXT: lxv vs3, 0(r3) 121; CHECK-NEXT: lxv vs2, 16(r3) 122; CHECK-NEXT: xxmtacc acc0 123; CHECK-NEXT: xvi16ger2pp acc0, v2, v2 124; CHECK-NEXT: xxmfacc acc0 125; CHECK-NEXT: stxv vs0, 48(r7) 126; CHECK-NEXT: stxv vs1, 32(r7) 127; CHECK-NEXT: stxv vs2, 16(r7) 128; CHECK-NEXT: stxv vs3, 0(r7) 129; CHECK-NEXT: blr 130; 131; CHECK-BE-LABEL: test4: 132; CHECK-BE: # %bb.0: # %entry 133; CHECK-BE-NEXT: lxv vs1, 16(r3) 134; CHECK-BE-NEXT: lxv vs0, 0(r3) 135; CHECK-BE-NEXT: lxv vs3, 48(r3) 136; CHECK-BE-NEXT: lxv vs2, 32(r3) 137; CHECK-BE-NEXT: xxmtacc acc0 138; CHECK-BE-NEXT: xvi16ger2pp acc0, v2, v2 139; CHECK-BE-NEXT: xxmfacc acc0 140; CHECK-BE-NEXT: stxv vs1, 16(r7) 141; CHECK-BE-NEXT: stxv vs0, 0(r7) 142; CHECK-BE-NEXT: stxv vs3, 48(r7) 143; CHECK-BE-NEXT: stxv vs2, 32(r7) 144; CHECK-BE-NEXT: blr 145entry: 146 %0 = bitcast i8* %vqp to <512 x i1>* 147 %1 = load <512 x i1>, <512 x i1>* %0, align 64 148 %2 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc) 149 %3 = bitcast i8* %resp to <512 x i1>* 150 store <512 x i1> %2, <512 x i1>* %3, align 64 151 ret void 152} 153 154; Function Attrs: nounwind readnone 155declare <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>) 156 157; Function Attrs: nofree nounwind 158define dso_local void @test5(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { 159; CHECK-LABEL: test5: 160; CHECK: # %bb.0: # %entry 161; CHECK-NEXT: lxv vs1, 32(r3) 162; CHECK-NEXT: lxv vs0, 48(r3) 163; CHECK-NEXT: lxv vs3, 0(r3) 164; CHECK-NEXT: lxv vs2, 16(r3) 165; CHECK-NEXT: xxmtacc acc0 166; CHECK-NEXT: pmxvi8ger4spp acc0, v2, v2, 0, 0, 0 167; CHECK-NEXT: xxmfacc acc0 168; CHECK-NEXT: stxv vs0, 48(r7) 169; CHECK-NEXT: stxv vs1, 32(r7) 170; CHECK-NEXT: stxv vs2, 16(r7) 171; CHECK-NEXT: stxv vs3, 0(r7) 172; CHECK-NEXT: blr 173; 174; CHECK-BE-LABEL: test5: 175; CHECK-BE: # %bb.0: # %entry 176; CHECK-BE-NEXT: lxv vs1, 16(r3) 177; CHECK-BE-NEXT: lxv vs0, 0(r3) 178; CHECK-BE-NEXT: lxv vs3, 48(r3) 179; CHECK-BE-NEXT: lxv vs2, 32(r3) 180; CHECK-BE-NEXT: xxmtacc acc0 181; CHECK-BE-NEXT: pmxvi8ger4spp acc0, v2, v2, 0, 0, 0 182; CHECK-BE-NEXT: xxmfacc acc0 183; CHECK-BE-NEXT: stxv vs1, 16(r7) 184; CHECK-BE-NEXT: stxv vs0, 0(r7) 185; CHECK-BE-NEXT: stxv vs3, 48(r7) 186; CHECK-BE-NEXT: stxv vs2, 32(r7) 187; CHECK-BE-NEXT: blr 188entry: 189 %0 = bitcast i8* %vqp to <512 x i1>* 190 %1 = load <512 x i1>, <512 x i1>* %0, align 64 191 %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) 192 %3 = bitcast i8* %resp to <512 x i1>* 193 store <512 x i1> %2, <512 x i1>* %3, align 64 194 ret void 195} 196 197; Function Attrs: nounwind readnone 198declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) 199 200; Function Attrs: nofree nounwind 201define dso_local void @test6(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) { 202; CHECK-LABEL: test6: 203; CHECK: # %bb.0: # %entry 204; CHECK-NEXT: lxv vs1, 32(r3) 205; CHECK-NEXT: lxv vs0, 48(r3) 206; CHECK-NEXT: lxv vs3, 0(r3) 207; CHECK-NEXT: lxv vs2, 16(r3) 208; CHECK-NEXT: xxmtacc acc0 209; CHECK-NEXT: pmxvi16ger2pp acc0, v2, v2, 0, 0, 0 210; CHECK-NEXT: xxmfacc acc0 211; CHECK-NEXT: stxv vs0, 48(r7) 212; CHECK-NEXT: stxv vs1, 32(r7) 213; CHECK-NEXT: stxv vs2, 16(r7) 214; CHECK-NEXT: stxv vs3, 0(r7) 215; CHECK-NEXT: blr 216; 217; CHECK-BE-LABEL: test6: 218; CHECK-BE: # %bb.0: # %entry 219; CHECK-BE-NEXT: lxv vs1, 16(r3) 220; CHECK-BE-NEXT: lxv vs0, 0(r3) 221; CHECK-BE-NEXT: lxv vs3, 48(r3) 222; CHECK-BE-NEXT: lxv vs2, 32(r3) 223; CHECK-BE-NEXT: xxmtacc acc0 224; CHECK-BE-NEXT: pmxvi16ger2pp acc0, v2, v2, 0, 0, 0 225; CHECK-BE-NEXT: xxmfacc acc0 226; CHECK-BE-NEXT: stxv vs1, 16(r7) 227; CHECK-BE-NEXT: stxv vs0, 0(r7) 228; CHECK-BE-NEXT: stxv vs3, 48(r7) 229; CHECK-BE-NEXT: stxv vs2, 32(r7) 230; CHECK-BE-NEXT: blr 231entry: 232 %0 = bitcast i8* %vqp to <512 x i1>* 233 %1 = load <512 x i1>, <512 x i1>* %0, align 64 234 %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) 235 %3 = bitcast i8* %resp to <512 x i1>* 236 store <512 x i1> %2, <512 x i1>* %3, align 64 237 ret void 238} 239 240; Function Attrs: nounwind readnone 241declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) 242