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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN:   FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN:   FileCheck %s
8
9; These test cases aim to test the vector string isolate builtins on Power10.
10
11declare <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8>, i32)
12declare <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8>, i32)
13
14define <16 x i8> @test_vclrlb(<16 x i8> %a, i32 %n) {
15; CHECK-LABEL: test_vclrlb:
16; CHECK:       # %bb.0: # %entry
17; CHECK-NEXT:    vclrlb v2, v2, r5
18; CHECK-NEXT:    blr
19entry:
20  %tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8> %a, i32 %n)
21  ret <16 x i8> %tmp
22}
23
24define <16 x i8> @test_vclrrb(<16 x i8> %a, i32 %n) {
25; CHECK-LABEL: test_vclrrb:
26; CHECK:       # %bb.0: # %entry
27; CHECK-NEXT:    vclrrb v2, v2, r5
28; CHECK-NEXT:    blr
29entry:
30  %tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8> %a, i32 %n)
31  ret <16 x i8> %tmp
32}
33
34declare <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8>)
35declare <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>)
36declare <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16>)
37declare <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16>)
38
39declare i32 @llvm.ppc.altivec.vstribr.p(i32, <16 x i8>)
40declare i32 @llvm.ppc.altivec.vstribl.p(i32, <16 x i8>)
41declare i32 @llvm.ppc.altivec.vstrihr.p(i32, <8 x i16>)
42declare i32 @llvm.ppc.altivec.vstrihl.p(i32, <8 x i16>)
43
44define <16 x i8> @test_vstribr(<16 x i8> %a) {
45; CHECK-LABEL: test_vstribr:
46; CHECK:       # %bb.0: # %entry
47; CHECK-NEXT:    vstribr v2, v2
48; CHECK-NEXT:    blr
49entry:
50  %tmp = tail call <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8> %a)
51  ret <16 x i8> %tmp
52}
53
54define <16 x i8> @test_vstribl(<16 x i8> %a) {
55; CHECK-LABEL: test_vstribl:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    vstribl v2, v2
58; CHECK-NEXT:    blr
59entry:
60  %tmp = tail call <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>%a)
61  ret <16 x i8> %tmp
62}
63
64define <8 x i16> @test_vstrihr(<8 x i16> %a) {
65; CHECK-LABEL: test_vstrihr:
66; CHECK:       # %bb.0: # %entry
67; CHECK-NEXT:    vstrihr v2, v2
68; CHECK-NEXT:    blr
69entry:
70  %tmp = tail call <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16> %a)
71  ret <8 x i16> %tmp
72}
73
74define <8 x i16> @test_vstrihl(<8 x i16> %a) {
75; CHECK-LABEL: test_vstrihl:
76; CHECK:       # %bb.0: # %entry
77; CHECK-NEXT:    vstrihl v2, v2
78; CHECK-NEXT:    blr
79entry:
80  %tmp = tail call <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16> %a)
81  ret <8 x i16> %tmp
82}
83
84define i32 @test_vstribr_p(<16 x i8> %a) {
85; CHECK-LABEL: test_vstribr_p:
86; CHECK:       # %bb.0: # %entry
87; CHECK-NEXT:    vstribr. v2, v2
88; CHECK-NEXT:    setbc r3, 4*cr6+eq
89; CHECK-NEXT:    blr
90entry:
91  %tmp = tail call i32 @llvm.ppc.altivec.vstribr.p(i32 1, <16 x i8> %a)
92  ret i32 %tmp
93}
94
95define i32 @test_vstribl_p(<16 x i8> %a) {
96; CHECK-LABEL: test_vstribl_p:
97; CHECK:       # %bb.0: # %entry
98; CHECK-NEXT:    vstribl. v2, v2
99; CHECK-NEXT:    setbc r3, 4*cr6+eq
100; CHECK-NEXT:    blr
101entry:
102  %tmp = tail call i32 @llvm.ppc.altivec.vstribl.p(i32 1, <16 x i8> %a)
103  ret i32 %tmp
104}
105
106define i32 @test_vstrihr_p(<8 x i16> %a) {
107; CHECK-LABEL: test_vstrihr_p:
108; CHECK:       # %bb.0: # %entry
109; CHECK-NEXT:    vstrihr. v2, v2
110; CHECK-NEXT:    setbc r3, 4*cr6+eq
111; CHECK-NEXT:    blr
112entry:
113  %tmp = tail call i32 @llvm.ppc.altivec.vstrihr.p(i32 1, <8 x i16> %a)
114  ret i32 %tmp
115}
116
117define i32 @test_vstrihl_p(<8 x i16> %a) {
118; CHECK-LABEL: test_vstrihl_p:
119; CHECK:       # %bb.0: # %entry
120; CHECK-NEXT:    vstrihl. v2, v2
121; CHECK-NEXT:    setbc r3, 4*cr6+eq
122; CHECK-NEXT:    blr
123entry:
124  %tmp = tail call i32 @llvm.ppc.altivec.vstrihl.p(i32 1, <8 x i16> %a)
125  ret i32 %tmp
126}
127