1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s 5 6; This test case aims to test vector sign extend builtins. 7 8declare <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64>) nounwind readnone 9 10define <1 x i128> @test_vextsd2q(<2 x i64> %x) nounwind readnone { 11; CHECK-LABEL: test_vextsd2q: 12; CHECK: # %bb.0: 13; CHECK-NEXT: vextsd2q v2, v2 14; CHECK-NEXT: blr 15 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64> %x) 16 ret <1 x i128> %tmp 17} 18