1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s 5 6; These test cases aim to test the VSX PCV Generate Operations on Power10. 7 8declare <16 x i8> @llvm.ppc.vsx.xxgenpcvbm(<16 x i8>, i32) 9declare <8 x i16> @llvm.ppc.vsx.xxgenpcvhm(<8 x i16>, i32) 10declare <4 x i32> @llvm.ppc.vsx.xxgenpcvwm(<4 x i32>, i32) 11declare <2 x i64> @llvm.ppc.vsx.xxgenpcvdm(<2 x i64>, i32) 12 13define <16 x i8> @test_xxgenpcvbm(<16 x i8> %a) { 14; CHECK-LABEL: test_xxgenpcvbm: 15; CHECK: # %bb.0: # %entry 16; CHECK-NEXT: xxgenpcvbm v2, v2, 1 17; CHECK-NEXT: blr 18entry: 19 %gen = tail call <16 x i8> @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %a, i32 1) 20 ret <16 x i8> %gen 21} 22 23define <8 x i16> @test_xxgenpcvhm(<8 x i16> %a) { 24; CHECK-LABEL: test_xxgenpcvhm: 25; CHECK: # %bb.0: # %entry 26; CHECK-NEXT: xxgenpcvhm v2, v2, 1 27; CHECK-NEXT: blr 28entry: 29 %gen = tail call <8 x i16> @llvm.ppc.vsx.xxgenpcvhm(<8 x i16> %a, i32 1) 30 ret <8 x i16> %gen 31} 32 33define <4 x i32> @test_xxgenpcvwm(<4 x i32> %a) { 34; CHECK-LABEL: test_xxgenpcvwm: 35; CHECK: # %bb.0: # %entry 36; CHECK-NEXT: xxgenpcvwm v2, v2, 1 37; CHECK-NEXT: blr 38entry: 39 %gen = tail call <4 x i32> @llvm.ppc.vsx.xxgenpcvwm(<4 x i32> %a, i32 1) 40 ret <4 x i32> %gen 41} 42 43define <2 x i64> @test_xxgenpcvdm(<2 x i64> %a) { 44; CHECK-LABEL: test_xxgenpcvdm: 45; CHECK: # %bb.0: # %entry 46; CHECK-NEXT: xxgenpcvdm v2, v2, 1 47; CHECK-NEXT: blr 48entry: 49 %gen = tail call <2 x i64> @llvm.ppc.vsx.xxgenpcvdm(<2 x i64> %a, i32 1) 50 ret <2 x i64> %gen 51} 52