1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE 3; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE 4 5@as = local_unnamed_addr global i16 0, align 2 6@bs = local_unnamed_addr global i16 0, align 2 7@ai = local_unnamed_addr global i32 0, align 4 8@bi = local_unnamed_addr global i32 0, align 4 9 10define void @bswapStorei64Toi32() { 11; CHECK-LABEL: bswapStorei64Toi32: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: addis 3, 2, ai@toc@ha 14; CHECK-NEXT: addis 4, 2, bi@toc@ha 15; CHECK-NEXT: lwa 3, ai@toc@l(3) 16; CHECK-NEXT: addi 4, 4, bi@toc@l 17; CHECK-NEXT: rldicl 3, 3, 32, 32 18; CHECK-NEXT: stwbrx 3, 0, 4 19; CHECK-NEXT: blr 20; CHECK-LE-LABEL: bswapStorei64Toi32: 21; CHECK-LE: # %bb.0: # %entry 22; CHECK-LE-NEXT: addis 3, 2, ai@toc@ha 23; CHECK-LE-NEXT: addis 4, 2, bi@toc@ha 24; CHECK-LE-NEXT: lwa 3, ai@toc@l(3) 25; CHECK-LE-NEXT: addi 4, 4, bi@toc@l 26; CHECK-LE-NEXT: rldicl 3, 3, 32, 32 27; CHECK-LE-NEXT: stwbrx 3, 0, 4 28; CHECK-LE-NEXT: blr 29; 30; CHECK-BE-LABEL: bswapStorei64Toi32: 31; CHECK-BE: # %bb.0: # %entry 32; CHECK-BE-NEXT: addis 3, 2, .LC0@toc@ha 33; CHECK-BE-NEXT: addis 4, 2, .LC1@toc@ha 34; CHECK-BE-NEXT: ld 3, .LC0@toc@l(3) 35; CHECK-BE-NEXT: ld 4, .LC1@toc@l(4) 36; CHECK-BE-NEXT: lwa 3, 0(3) 37; CHECK-BE-NEXT: rldicl 3, 3, 32, 32 38; CHECK-BE-NEXT: stwbrx 3, 0, 4 39; CHECK-BE-NEXT: blr 40entry: 41 %0 = load i32, i32* @ai, align 4 42 %conv.i = sext i32 %0 to i64 43 %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i) 44 %conv = trunc i64 %or26.i to i32 45 store i32 %conv, i32* @bi, align 4 46 ret void 47} 48 49define void @bswapStorei32Toi16() { 50; CHECK-LABEL: bswapStorei32Toi16: 51; CHECK: # %bb.0: # %entry 52; CHECK-NEXT: addis 3, 2, as@toc@ha 53; CHECK-NEXT: addis 4, 2, bs@toc@ha 54; CHECK-NEXT: lha 3, as@toc@l(3) 55; CHECK-NEXT: addi 4, 4, bs@toc@l 56; CHECK-NEXT: srwi 3, 3, 16 57; CHECK-NEXT: sthbrx 3, 0, 4 58; CHECK-NEXT: blr 59; CHECK-LE-LABEL: bswapStorei32Toi16: 60; CHECK-LE: # %bb.0: # %entry 61; CHECK-LE-NEXT: addis 3, 2, as@toc@ha 62; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha 63; CHECK-LE-NEXT: lha 3, as@toc@l(3) 64; CHECK-LE-NEXT: addi 4, 4, bs@toc@l 65; CHECK-LE-NEXT: srwi 3, 3, 16 66; CHECK-LE-NEXT: sthbrx 3, 0, 4 67; CHECK-LE-NEXT: blr 68; 69; CHECK-BE-LABEL: bswapStorei32Toi16: 70; CHECK-BE: # %bb.0: # %entry 71; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha 72; CHECK-BE-NEXT: addis 4, 2, .LC3@toc@ha 73; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3) 74; CHECK-BE-NEXT: ld 4, .LC3@toc@l(4) 75; CHECK-BE-NEXT: lha 3, 0(3) 76; CHECK-BE-NEXT: srwi 3, 3, 16 77; CHECK-BE-NEXT: sthbrx 3, 0, 4 78; CHECK-BE-NEXT: blr 79entry: 80 %0 = load i16, i16* @as, align 2 81 %conv.i = sext i16 %0 to i32 82 %or26.i = tail call i32 @llvm.bswap.i32(i32 %conv.i) 83 %conv = trunc i32 %or26.i to i16 84 store i16 %conv, i16* @bs, align 2 85 ret void 86} 87 88define void @bswapStorei64Toi16() { 89; CHECK-LABEL: bswapStorei64Toi16: 90; CHECK: # %bb.0: # %entry 91; CHECK-NEXT: addis 3, 2, as@toc@ha 92; CHECK-NEXT: addis 4, 2, bs@toc@ha 93; CHECK-NEXT: lha 3, as@toc@l(3) 94; CHECK-NEXT: addi 4, 4, bs@toc@l 95; CHECK-NEXT: rldicl 3, 3, 16, 48 96; CHECK-NEXT: sthbrx 3, 0, 4 97; CHECK-NEXT: blr 98; CHECK-LE-LABEL: bswapStorei64Toi16: 99; CHECK-LE: # %bb.0: # %entry 100; CHECK-LE-NEXT: addis 3, 2, as@toc@ha 101; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha 102; CHECK-LE-NEXT: lha 3, as@toc@l(3) 103; CHECK-LE-NEXT: addi 4, 4, bs@toc@l 104; CHECK-LE-NEXT: rldicl 3, 3, 16, 48 105; CHECK-LE-NEXT: sthbrx 3, 0, 4 106; CHECK-LE-NEXT: blr 107; 108; CHECK-BE-LABEL: bswapStorei64Toi16: 109; CHECK-BE: # %bb.0: # %entry 110; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha 111; CHECK-BE-NEXT: addis 4, 2, .LC3@toc@ha 112; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3) 113; CHECK-BE-NEXT: ld 4, .LC3@toc@l(4) 114; CHECK-BE-NEXT: lha 3, 0(3) 115; CHECK-BE-NEXT: rldicl 3, 3, 16, 48 116; CHECK-BE-NEXT: sthbrx 3, 0, 4 117; CHECK-BE-NEXT: blr 118entry: 119 %0 = load i16, i16* @as, align 2 120 %conv.i = sext i16 %0 to i64 121 %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i) 122 %conv = trunc i64 %or26.i to i16 123 store i16 %conv, i16* @bs, align 2 124 ret void 125} 126 127declare i32 @llvm.bswap.i32(i32) 128declare i64 @llvm.bswap.i64(i64) 129