1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s 3 4; There are at least 3 potential patterns corresponding to an unsigned saturated add: min, cmp with sum, cmp with not. 5; Test each of those patterns with i8/i16/i32/i64. 6; Test each of those with a constant operand and a variable operand. 7; Test each of those with a 128-bit vector type. 8 9define i8 @unsigned_sat_constant_i8_using_min(i8 %x) { 10; CHECK-LABEL: unsigned_sat_constant_i8_using_min: 11; CHECK: # %bb.0: 12; CHECK-NEXT: clrlwi 5, 3, 24 13; CHECK-NEXT: li 4, -43 14; CHECK-NEXT: cmplwi 5, 213 15; CHECK-NEXT: isellt 3, 3, 4 16; CHECK-NEXT: addi 3, 3, 42 17; CHECK-NEXT: blr 18 %c = icmp ult i8 %x, -43 19 %s = select i1 %c, i8 %x, i8 -43 20 %r = add i8 %s, 42 21 ret i8 %r 22} 23 24define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) { 25; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum: 26; CHECK: # %bb.0: 27; CHECK-NEXT: clrlwi 3, 3, 24 28; CHECK-NEXT: addi 3, 3, 42 29; CHECK-NEXT: andi. 4, 3, 256 30; CHECK-NEXT: li 4, -1 31; CHECK-NEXT: iseleq 3, 3, 4 32; CHECK-NEXT: blr 33 %a = add i8 %x, 42 34 %c = icmp ugt i8 %x, %a 35 %r = select i1 %c, i8 -1, i8 %a 36 ret i8 %r 37} 38 39define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) { 40; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_notval: 41; CHECK: # %bb.0: 42; CHECK-NEXT: clrlwi 5, 3, 24 43; CHECK-NEXT: li 4, -1 44; CHECK-NEXT: addi 3, 3, 42 45; CHECK-NEXT: cmplwi 5, 213 46; CHECK-NEXT: iselgt 3, 4, 3 47; CHECK-NEXT: blr 48 %a = add i8 %x, 42 49 %c = icmp ugt i8 %x, -43 50 %r = select i1 %c, i8 -1, i8 %a 51 ret i8 %r 52} 53 54define i16 @unsigned_sat_constant_i16_using_min(i16 %x) { 55; CHECK-LABEL: unsigned_sat_constant_i16_using_min: 56; CHECK: # %bb.0: 57; CHECK-NEXT: clrlwi 5, 3, 16 58; CHECK-NEXT: li 4, -43 59; CHECK-NEXT: cmplwi 5, 65493 60; CHECK-NEXT: isellt 3, 3, 4 61; CHECK-NEXT: addi 3, 3, 42 62; CHECK-NEXT: blr 63 %c = icmp ult i16 %x, -43 64 %s = select i1 %c, i16 %x, i16 -43 65 %r = add i16 %s, 42 66 ret i16 %r 67} 68 69define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) { 70; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum: 71; CHECK: # %bb.0: 72; CHECK-NEXT: clrlwi 3, 3, 16 73; CHECK-NEXT: addi 3, 3, 42 74; CHECK-NEXT: andis. 4, 3, 1 75; CHECK-NEXT: li 4, -1 76; CHECK-NEXT: iseleq 3, 3, 4 77; CHECK-NEXT: blr 78 %a = add i16 %x, 42 79 %c = icmp ugt i16 %x, %a 80 %r = select i1 %c, i16 -1, i16 %a 81 ret i16 %r 82} 83 84define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) { 85; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_notval: 86; CHECK: # %bb.0: 87; CHECK-NEXT: clrlwi 5, 3, 16 88; CHECK-NEXT: li 4, -1 89; CHECK-NEXT: addi 3, 3, 42 90; CHECK-NEXT: cmplwi 5, 65493 91; CHECK-NEXT: iselgt 3, 4, 3 92; CHECK-NEXT: blr 93 %a = add i16 %x, 42 94 %c = icmp ugt i16 %x, -43 95 %r = select i1 %c, i16 -1, i16 %a 96 ret i16 %r 97} 98 99define i32 @unsigned_sat_constant_i32_using_min(i32 %x) { 100; CHECK-LABEL: unsigned_sat_constant_i32_using_min: 101; CHECK: # %bb.0: 102; CHECK-NEXT: li 4, -43 103; CHECK-NEXT: cmplw 3, 4 104; CHECK-NEXT: isellt 3, 3, 4 105; CHECK-NEXT: addi 3, 3, 42 106; CHECK-NEXT: blr 107 %c = icmp ult i32 %x, -43 108 %s = select i1 %c, i32 %x, i32 -43 109 %r = add i32 %s, 42 110 ret i32 %r 111} 112 113define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) { 114; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum: 115; CHECK: # %bb.0: 116; CHECK-NEXT: addi 5, 3, 42 117; CHECK-NEXT: li 4, -1 118; CHECK-NEXT: cmplw 5, 3 119; CHECK-NEXT: isellt 3, 4, 5 120; CHECK-NEXT: blr 121 %a = add i32 %x, 42 122 %c = icmp ugt i32 %x, %a 123 %r = select i1 %c, i32 -1, i32 %a 124 ret i32 %r 125} 126 127define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) { 128; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval: 129; CHECK: # %bb.0: 130; CHECK-NEXT: li 4, -43 131; CHECK-NEXT: addi 5, 3, 42 132; CHECK-NEXT: cmplw 3, 4 133; CHECK-NEXT: li 3, -1 134; CHECK-NEXT: iselgt 3, 3, 5 135; CHECK-NEXT: blr 136 %a = add i32 %x, 42 137 %c = icmp ugt i32 %x, -43 138 %r = select i1 %c, i32 -1, i32 %a 139 ret i32 %r 140} 141 142define i64 @unsigned_sat_constant_i64_using_min(i64 %x) { 143; CHECK-LABEL: unsigned_sat_constant_i64_using_min: 144; CHECK: # %bb.0: 145; CHECK-NEXT: li 4, -43 146; CHECK-NEXT: cmpld 3, 4 147; CHECK-NEXT: isellt 3, 3, 4 148; CHECK-NEXT: addi 3, 3, 42 149; CHECK-NEXT: blr 150 %c = icmp ult i64 %x, -43 151 %s = select i1 %c, i64 %x, i64 -43 152 %r = add i64 %s, 42 153 ret i64 %r 154} 155 156define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) { 157; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_sum: 158; CHECK: # %bb.0: 159; CHECK-NEXT: addi 5, 3, 42 160; CHECK-NEXT: li 4, -1 161; CHECK-NEXT: cmpld 5, 3 162; CHECK-NEXT: isellt 3, 4, 5 163; CHECK-NEXT: blr 164 %a = add i64 %x, 42 165 %c = icmp ugt i64 %x, %a 166 %r = select i1 %c, i64 -1, i64 %a 167 ret i64 %r 168} 169 170define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) { 171; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_notval: 172; CHECK: # %bb.0: 173; CHECK-NEXT: li 4, -43 174; CHECK-NEXT: addi 5, 3, 42 175; CHECK-NEXT: cmpld 3, 4 176; CHECK-NEXT: li 3, -1 177; CHECK-NEXT: iselgt 3, 3, 5 178; CHECK-NEXT: blr 179 %a = add i64 %x, 42 180 %c = icmp ugt i64 %x, -43 181 %r = select i1 %c, i64 -1, i64 %a 182 ret i64 %r 183} 184 185define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) { 186; CHECK-LABEL: unsigned_sat_variable_i8_using_min: 187; CHECK: # %bb.0: 188; CHECK-NEXT: not 5, 4 189; CHECK-NEXT: clrlwi 6, 3, 24 190; CHECK-NEXT: clrlwi 7, 5, 24 191; CHECK-NEXT: cmplw 6, 7 192; CHECK-NEXT: isellt 3, 3, 5 193; CHECK-NEXT: add 3, 3, 4 194; CHECK-NEXT: blr 195 %noty = xor i8 %y, -1 196 %c = icmp ult i8 %x, %noty 197 %s = select i1 %c, i8 %x, i8 %noty 198 %r = add i8 %s, %y 199 ret i8 %r 200} 201 202define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) { 203; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum: 204; CHECK: # %bb.0: 205; CHECK-NEXT: clrlwi 4, 4, 24 206; CHECK-NEXT: clrlwi 3, 3, 24 207; CHECK-NEXT: add 3, 3, 4 208; CHECK-NEXT: andi. 4, 3, 256 209; CHECK-NEXT: li 4, -1 210; CHECK-NEXT: iseleq 3, 3, 4 211; CHECK-NEXT: blr 212 %a = add i8 %x, %y 213 %c = icmp ugt i8 %x, %a 214 %r = select i1 %c, i8 -1, i8 %a 215 ret i8 %r 216} 217 218define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) { 219; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval: 220; CHECK: # %bb.0: 221; CHECK-NEXT: not 6, 4 222; CHECK-NEXT: clrlwi 7, 3, 24 223; CHECK-NEXT: li 5, -1 224; CHECK-NEXT: add 3, 3, 4 225; CHECK-NEXT: clrlwi 6, 6, 24 226; CHECK-NEXT: cmplw 7, 6 227; CHECK-NEXT: iselgt 3, 5, 3 228; CHECK-NEXT: blr 229 %noty = xor i8 %y, -1 230 %a = add i8 %x, %y 231 %c = icmp ugt i8 %x, %noty 232 %r = select i1 %c, i8 -1, i8 %a 233 ret i8 %r 234} 235 236define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) { 237; CHECK-LABEL: unsigned_sat_variable_i16_using_min: 238; CHECK: # %bb.0: 239; CHECK-NEXT: not 5, 4 240; CHECK-NEXT: clrlwi 6, 3, 16 241; CHECK-NEXT: clrlwi 7, 5, 16 242; CHECK-NEXT: cmplw 6, 7 243; CHECK-NEXT: isellt 3, 3, 5 244; CHECK-NEXT: add 3, 3, 4 245; CHECK-NEXT: blr 246 %noty = xor i16 %y, -1 247 %c = icmp ult i16 %x, %noty 248 %s = select i1 %c, i16 %x, i16 %noty 249 %r = add i16 %s, %y 250 ret i16 %r 251} 252 253define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) { 254; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum: 255; CHECK: # %bb.0: 256; CHECK-NEXT: clrlwi 4, 4, 16 257; CHECK-NEXT: clrlwi 3, 3, 16 258; CHECK-NEXT: add 3, 3, 4 259; CHECK-NEXT: andis. 4, 3, 1 260; CHECK-NEXT: li 4, -1 261; CHECK-NEXT: iseleq 3, 3, 4 262; CHECK-NEXT: blr 263 %a = add i16 %x, %y 264 %c = icmp ugt i16 %x, %a 265 %r = select i1 %c, i16 -1, i16 %a 266 ret i16 %r 267} 268 269define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) { 270; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval: 271; CHECK: # %bb.0: 272; CHECK-NEXT: not 6, 4 273; CHECK-NEXT: clrlwi 7, 3, 16 274; CHECK-NEXT: li 5, -1 275; CHECK-NEXT: add 3, 3, 4 276; CHECK-NEXT: clrlwi 6, 6, 16 277; CHECK-NEXT: cmplw 7, 6 278; CHECK-NEXT: iselgt 3, 5, 3 279; CHECK-NEXT: blr 280 %noty = xor i16 %y, -1 281 %a = add i16 %x, %y 282 %c = icmp ugt i16 %x, %noty 283 %r = select i1 %c, i16 -1, i16 %a 284 ret i16 %r 285} 286 287define i32 @unsigned_sat_variable_i32_using_min(i32 %x, i32 %y) { 288; CHECK-LABEL: unsigned_sat_variable_i32_using_min: 289; CHECK: # %bb.0: 290; CHECK-NEXT: not 5, 4 291; CHECK-NEXT: cmplw 3, 5 292; CHECK-NEXT: isellt 3, 3, 5 293; CHECK-NEXT: add 3, 3, 4 294; CHECK-NEXT: blr 295 %noty = xor i32 %y, -1 296 %c = icmp ult i32 %x, %noty 297 %s = select i1 %c, i32 %x, i32 %noty 298 %r = add i32 %s, %y 299 ret i32 %r 300} 301 302define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) { 303; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_sum: 304; CHECK: # %bb.0: 305; CHECK-NEXT: add 4, 3, 4 306; CHECK-NEXT: li 5, -1 307; CHECK-NEXT: cmplw 4, 3 308; CHECK-NEXT: isellt 3, 5, 4 309; CHECK-NEXT: blr 310 %a = add i32 %x, %y 311 %c = icmp ugt i32 %x, %a 312 %r = select i1 %c, i32 -1, i32 %a 313 ret i32 %r 314} 315 316define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) { 317; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval: 318; CHECK: # %bb.0: 319; CHECK-NEXT: not 6, 4 320; CHECK-NEXT: li 5, -1 321; CHECK-NEXT: cmplw 3, 6 322; CHECK-NEXT: add 3, 3, 4 323; CHECK-NEXT: iselgt 3, 5, 3 324; CHECK-NEXT: blr 325 %noty = xor i32 %y, -1 326 %a = add i32 %x, %y 327 %c = icmp ugt i32 %x, %noty 328 %r = select i1 %c, i32 -1, i32 %a 329 ret i32 %r 330} 331 332define i64 @unsigned_sat_variable_i64_using_min(i64 %x, i64 %y) { 333; CHECK-LABEL: unsigned_sat_variable_i64_using_min: 334; CHECK: # %bb.0: 335; CHECK-NEXT: not 5, 4 336; CHECK-NEXT: cmpld 3, 5 337; CHECK-NEXT: isellt 3, 3, 5 338; CHECK-NEXT: add 3, 3, 4 339; CHECK-NEXT: blr 340 %noty = xor i64 %y, -1 341 %c = icmp ult i64 %x, %noty 342 %s = select i1 %c, i64 %x, i64 %noty 343 %r = add i64 %s, %y 344 ret i64 %r 345} 346 347define i64 @unsigned_sat_variable_i64_using_cmp_sum(i64 %x, i64 %y) { 348; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_sum: 349; CHECK: # %bb.0: 350; CHECK-NEXT: add 4, 3, 4 351; CHECK-NEXT: li 5, -1 352; CHECK-NEXT: cmpld 4, 3 353; CHECK-NEXT: isellt 3, 5, 4 354; CHECK-NEXT: blr 355 %a = add i64 %x, %y 356 %c = icmp ugt i64 %x, %a 357 %r = select i1 %c, i64 -1, i64 %a 358 ret i64 %r 359} 360 361define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) { 362; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_notval: 363; CHECK: # %bb.0: 364; CHECK-NEXT: not 6, 4 365; CHECK-NEXT: li 5, -1 366; CHECK-NEXT: cmpld 3, 6 367; CHECK-NEXT: add 3, 3, 4 368; CHECK-NEXT: iselgt 3, 5, 3 369; CHECK-NEXT: blr 370 %noty = xor i64 %y, -1 371 %a = add i64 %x, %y 372 %c = icmp ugt i64 %x, %noty 373 %r = select i1 %c, i64 -1, i64 %a 374 ret i64 %r 375} 376 377define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) { 378; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min: 379; CHECK: # %bb.0: 380; CHECK-NEXT: addis 3, 2, .LCPI24_0@toc@ha 381; CHECK-NEXT: addi 3, 3, .LCPI24_0@toc@l 382; CHECK-NEXT: lvx 3, 0, 3 383; CHECK-NEXT: addis 3, 2, .LCPI24_1@toc@ha 384; CHECK-NEXT: addi 3, 3, .LCPI24_1@toc@l 385; CHECK-NEXT: vminub 2, 2, 3 386; CHECK-NEXT: lvx 3, 0, 3 387; CHECK-NEXT: vaddubm 2, 2, 3 388; CHECK-NEXT: blr 389 %c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> 390 %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> 391 %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42> 392 ret <16 x i8> %r 393} 394 395define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) { 396; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum: 397; CHECK: # %bb.0: 398; CHECK-NEXT: addis 3, 2, .LCPI25_0@toc@ha 399; CHECK-NEXT: addi 3, 3, .LCPI25_0@toc@l 400; CHECK-NEXT: lvx 3, 0, 3 401; CHECK-NEXT: vaddubs 2, 2, 3 402; CHECK-NEXT: blr 403 %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42> 404 %c = icmp ugt <16 x i8> %x, %a 405 %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a 406 ret <16 x i8> %r 407} 408 409define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) { 410; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval: 411; CHECK: # %bb.0: 412; CHECK-NEXT: addis 3, 2, .LCPI26_0@toc@ha 413; CHECK-NEXT: addi 3, 3, .LCPI26_0@toc@l 414; CHECK-NEXT: lvx 3, 0, 3 415; CHECK-NEXT: vaddubs 2, 2, 3 416; CHECK-NEXT: blr 417 %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42> 418 %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> 419 %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a 420 ret <16 x i8> %r 421} 422 423define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) { 424; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min: 425; CHECK: # %bb.0: 426; CHECK-NEXT: addis 3, 2, .LCPI27_0@toc@ha 427; CHECK-NEXT: addi 3, 3, .LCPI27_0@toc@l 428; CHECK-NEXT: lvx 3, 0, 3 429; CHECK-NEXT: addis 3, 2, .LCPI27_1@toc@ha 430; CHECK-NEXT: addi 3, 3, .LCPI27_1@toc@l 431; CHECK-NEXT: vminuh 2, 2, 3 432; CHECK-NEXT: lvx 3, 0, 3 433; CHECK-NEXT: vadduhm 2, 2, 3 434; CHECK-NEXT: blr 435 %c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43> 436 %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43> 437 %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42> 438 ret <8 x i16> %r 439} 440 441define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) { 442; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum: 443; CHECK: # %bb.0: 444; CHECK-NEXT: addis 3, 2, .LCPI28_0@toc@ha 445; CHECK-NEXT: addi 3, 3, .LCPI28_0@toc@l 446; CHECK-NEXT: lvx 3, 0, 3 447; CHECK-NEXT: vadduhs 2, 2, 3 448; CHECK-NEXT: blr 449 %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42> 450 %c = icmp ugt <8 x i16> %x, %a 451 %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a 452 ret <8 x i16> %r 453} 454 455define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) { 456; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval: 457; CHECK: # %bb.0: 458; CHECK-NEXT: addis 3, 2, .LCPI29_0@toc@ha 459; CHECK-NEXT: addi 3, 3, .LCPI29_0@toc@l 460; CHECK-NEXT: lvx 3, 0, 3 461; CHECK-NEXT: vadduhs 2, 2, 3 462; CHECK-NEXT: blr 463 %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42> 464 %c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43> 465 %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a 466 ret <8 x i16> %r 467} 468 469define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) { 470; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min: 471; CHECK: # %bb.0: 472; CHECK-NEXT: addis 3, 2, .LCPI30_0@toc@ha 473; CHECK-NEXT: addi 3, 3, .LCPI30_0@toc@l 474; CHECK-NEXT: lvx 3, 0, 3 475; CHECK-NEXT: addis 3, 2, .LCPI30_1@toc@ha 476; CHECK-NEXT: addi 3, 3, .LCPI30_1@toc@l 477; CHECK-NEXT: vminuw 2, 2, 3 478; CHECK-NEXT: lvx 3, 0, 3 479; CHECK-NEXT: vadduwm 2, 2, 3 480; CHECK-NEXT: blr 481 %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43> 482 %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43> 483 %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42> 484 ret <4 x i32> %r 485} 486 487define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) { 488; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum: 489; CHECK: # %bb.0: 490; CHECK-NEXT: addis 3, 2, .LCPI31_0@toc@ha 491; CHECK-NEXT: addi 3, 3, .LCPI31_0@toc@l 492; CHECK-NEXT: lvx 3, 0, 3 493; CHECK-NEXT: vadduws 2, 2, 3 494; CHECK-NEXT: blr 495 %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> 496 %c = icmp ugt <4 x i32> %x, %a 497 %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a 498 ret <4 x i32> %r 499} 500 501define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) { 502; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval: 503; CHECK: # %bb.0: 504; CHECK-NEXT: addis 3, 2, .LCPI32_0@toc@ha 505; CHECK-NEXT: addi 3, 3, .LCPI32_0@toc@l 506; CHECK-NEXT: lvx 3, 0, 3 507; CHECK-NEXT: vadduws 2, 2, 3 508; CHECK-NEXT: blr 509 %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> 510 %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43> 511 %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a 512 ret <4 x i32> %r 513} 514 515define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) { 516; CHECK-LABEL: unsigned_sat_constant_v2i64_using_min: 517; CHECK: # %bb.0: 518; CHECK-NEXT: addis 3, 2, .LCPI33_0@toc@ha 519; CHECK-NEXT: addi 3, 3, .LCPI33_0@toc@l 520; CHECK-NEXT: lxvd2x 0, 0, 3 521; CHECK-NEXT: addis 3, 2, .LCPI33_1@toc@ha 522; CHECK-NEXT: addi 3, 3, .LCPI33_1@toc@l 523; CHECK-NEXT: xxswapd 35, 0 524; CHECK-NEXT: lxvd2x 0, 0, 3 525; CHECK-NEXT: vminud 2, 2, 3 526; CHECK-NEXT: xxswapd 35, 0 527; CHECK-NEXT: vaddudm 2, 2, 3 528; CHECK-NEXT: blr 529 %c = icmp ult <2 x i64> %x, <i64 -43, i64 -43> 530 %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43> 531 %r = add <2 x i64> %s, <i64 42, i64 42> 532 ret <2 x i64> %r 533} 534 535define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) { 536; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum: 537; CHECK: # %bb.0: 538; CHECK-NEXT: addis 3, 2, .LCPI34_0@toc@ha 539; CHECK-NEXT: addi 3, 3, .LCPI34_0@toc@l 540; CHECK-NEXT: lxvd2x 0, 0, 3 541; CHECK-NEXT: xxswapd 35, 0 542; CHECK-NEXT: xxleqv 0, 0, 0 543; CHECK-NEXT: vaddudm 3, 2, 3 544; CHECK-NEXT: vcmpgtud 2, 2, 3 545; CHECK-NEXT: xxsel 34, 35, 0, 34 546; CHECK-NEXT: blr 547 %a = add <2 x i64> %x, <i64 42, i64 42> 548 %c = icmp ugt <2 x i64> %x, %a 549 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a 550 ret <2 x i64> %r 551} 552 553define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) { 554; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval: 555; CHECK: # %bb.0: 556; CHECK-NEXT: addis 3, 2, .LCPI35_1@toc@ha 557; CHECK-NEXT: addi 3, 3, .LCPI35_1@toc@l 558; CHECK-NEXT: lxvd2x 0, 0, 3 559; CHECK-NEXT: addis 3, 2, .LCPI35_0@toc@ha 560; CHECK-NEXT: addi 3, 3, .LCPI35_0@toc@l 561; CHECK-NEXT: lxvd2x 1, 0, 3 562; CHECK-NEXT: xxswapd 35, 0 563; CHECK-NEXT: xxleqv 0, 0, 0 564; CHECK-NEXT: xxswapd 36, 1 565; CHECK-NEXT: vcmpgtud 3, 2, 3 566; CHECK-NEXT: vaddudm 2, 2, 4 567; CHECK-NEXT: xxsel 34, 34, 0, 35 568; CHECK-NEXT: blr 569 %a = add <2 x i64> %x, <i64 42, i64 42> 570 %c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43> 571 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a 572 ret <2 x i64> %r 573} 574 575define <16 x i8> @unsigned_sat_variable_v16i8_using_min(<16 x i8> %x, <16 x i8> %y) { 576; CHECK-LABEL: unsigned_sat_variable_v16i8_using_min: 577; CHECK: # %bb.0: 578; CHECK-NEXT: xxlnor 36, 35, 35 579; CHECK-NEXT: vminub 2, 2, 4 580; CHECK-NEXT: vaddubm 2, 2, 3 581; CHECK-NEXT: blr 582 %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 583 %c = icmp ult <16 x i8> %x, %noty 584 %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %noty 585 %r = add <16 x i8> %s, %y 586 ret <16 x i8> %r 587} 588 589define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x i8> %y) { 590; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum: 591; CHECK: # %bb.0: 592; CHECK-NEXT: vaddubs 2, 2, 3 593; CHECK-NEXT: blr 594 %a = add <16 x i8> %x, %y 595 %c = icmp ugt <16 x i8> %x, %a 596 %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a 597 ret <16 x i8> %r 598} 599 600define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16 x i8> %y) { 601; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval: 602; CHECK: # %bb.0: 603; CHECK-NEXT: xxlnor 36, 35, 35 604; CHECK-NEXT: xxleqv 0, 0, 0 605; CHECK-NEXT: vcmpgtub 4, 2, 4 606; CHECK-NEXT: vaddubm 2, 2, 3 607; CHECK-NEXT: xxsel 34, 34, 0, 36 608; CHECK-NEXT: blr 609 %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 610 %a = add <16 x i8> %x, %y 611 %c = icmp ugt <16 x i8> %x, %noty 612 %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a 613 ret <16 x i8> %r 614} 615 616define <8 x i16> @unsigned_sat_variable_v8i16_using_min(<8 x i16> %x, <8 x i16> %y) { 617; CHECK-LABEL: unsigned_sat_variable_v8i16_using_min: 618; CHECK: # %bb.0: 619; CHECK-NEXT: xxlnor 36, 35, 35 620; CHECK-NEXT: vminuh 2, 2, 4 621; CHECK-NEXT: vadduhm 2, 2, 3 622; CHECK-NEXT: blr 623 %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 624 %c = icmp ult <8 x i16> %x, %noty 625 %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %noty 626 %r = add <8 x i16> %s, %y 627 ret <8 x i16> %r 628} 629 630define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_sum(<8 x i16> %x, <8 x i16> %y) { 631; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum: 632; CHECK: # %bb.0: 633; CHECK-NEXT: vadduhs 2, 2, 3 634; CHECK-NEXT: blr 635 %a = add <8 x i16> %x, %y 636 %c = icmp ugt <8 x i16> %x, %a 637 %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a 638 ret <8 x i16> %r 639} 640 641define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8 x i16> %y) { 642; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval: 643; CHECK: # %bb.0: 644; CHECK-NEXT: xxlnor 36, 35, 35 645; CHECK-NEXT: xxleqv 0, 0, 0 646; CHECK-NEXT: vcmpgtuh 4, 2, 4 647; CHECK-NEXT: vadduhm 2, 2, 3 648; CHECK-NEXT: xxsel 34, 34, 0, 36 649; CHECK-NEXT: blr 650 %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 651 %a = add <8 x i16> %x, %y 652 %c = icmp ugt <8 x i16> %x, %noty 653 %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a 654 ret <8 x i16> %r 655} 656 657define <4 x i32> @unsigned_sat_variable_v4i32_using_min(<4 x i32> %x, <4 x i32> %y) { 658; CHECK-LABEL: unsigned_sat_variable_v4i32_using_min: 659; CHECK: # %bb.0: 660; CHECK-NEXT: xxlnor 36, 35, 35 661; CHECK-NEXT: vminuw 2, 2, 4 662; CHECK-NEXT: vadduwm 2, 2, 3 663; CHECK-NEXT: blr 664 %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1> 665 %c = icmp ult <4 x i32> %x, %noty 666 %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %noty 667 %r = add <4 x i32> %s, %y 668 ret <4 x i32> %r 669} 670 671define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i32> %y) { 672; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum: 673; CHECK: # %bb.0: 674; CHECK-NEXT: vadduws 2, 2, 3 675; CHECK-NEXT: blr 676 %a = add <4 x i32> %x, %y 677 %c = icmp ugt <4 x i32> %x, %a 678 %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a 679 ret <4 x i32> %r 680} 681 682define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4 x i32> %y) { 683; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval: 684; CHECK: # %bb.0: 685; CHECK-NEXT: xxlnor 36, 35, 35 686; CHECK-NEXT: xxleqv 0, 0, 0 687; CHECK-NEXT: vcmpgtuw 4, 2, 4 688; CHECK-NEXT: vadduwm 2, 2, 3 689; CHECK-NEXT: xxsel 34, 34, 0, 36 690; CHECK-NEXT: blr 691 %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1> 692 %a = add <4 x i32> %x, %y 693 %c = icmp ugt <4 x i32> %x, %noty 694 %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a 695 ret <4 x i32> %r 696} 697 698define <2 x i64> @unsigned_sat_variable_v2i64_using_min(<2 x i64> %x, <2 x i64> %y) { 699; CHECK-LABEL: unsigned_sat_variable_v2i64_using_min: 700; CHECK: # %bb.0: 701; CHECK-NEXT: xxlnor 36, 35, 35 702; CHECK-NEXT: vminud 2, 2, 4 703; CHECK-NEXT: vaddudm 2, 2, 3 704; CHECK-NEXT: blr 705 %noty = xor <2 x i64> %y, <i64 -1, i64 -1> 706 %c = icmp ult <2 x i64> %x, %noty 707 %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %noty 708 %r = add <2 x i64> %s, %y 709 ret <2 x i64> %r 710} 711 712define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i64> %y) { 713; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: 714; CHECK: # %bb.0: 715; CHECK-NEXT: vaddudm 3, 2, 3 716; CHECK-NEXT: xxleqv 0, 0, 0 717; CHECK-NEXT: vcmpgtud 2, 2, 3 718; CHECK-NEXT: xxsel 34, 35, 0, 34 719; CHECK-NEXT: blr 720 %a = add <2 x i64> %x, %y 721 %c = icmp ugt <2 x i64> %x, %a 722 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a 723 ret <2 x i64> %r 724} 725 726define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2 x i64> %y) { 727; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval: 728; CHECK: # %bb.0: 729; CHECK-NEXT: xxlnor 36, 35, 35 730; CHECK-NEXT: xxleqv 0, 0, 0 731; CHECK-NEXT: vcmpgtud 4, 2, 4 732; CHECK-NEXT: vaddudm 2, 2, 3 733; CHECK-NEXT: xxsel 34, 34, 0, 36 734; CHECK-NEXT: blr 735 %noty = xor <2 x i64> %y, <i64 -1, i64 -1> 736 %a = add <2 x i64> %x, %y 737 %c = icmp ugt <2 x i64> %x, %noty 738 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a 739 ret <2 x i64> %r 740} 741 742