1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ 3; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR9 %s 4; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ 5; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR8 %s 6; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown \ 7; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR7 %s 8 9define <1 x i64> @setcc_v1i128(<1 x i128> %a) { 10; CHECK-PWR9-LABEL: setcc_v1i128: 11; CHECK-PWR9: # %bb.0: # %entry 12; CHECK-PWR9-NEXT: mfvsrld r3, vs34 13; CHECK-PWR9-NEXT: cmpldi r3, 35708 14; CHECK-PWR9-NEXT: mfvsrd r3, vs34 15; CHECK-PWR9-NEXT: cmpdi cr1, r3, 0 16; CHECK-PWR9-NEXT: li r3, 1 17; CHECK-PWR9-NEXT: crnand 4*cr5+lt, 4*cr1+eq, lt 18; CHECK-PWR9-NEXT: isel r3, 0, r3, 4*cr5+lt 19; CHECK-PWR9-NEXT: blr 20; 21; CHECK-PWR8-LABEL: setcc_v1i128: 22; CHECK-PWR8: # %bb.0: # %entry 23; CHECK-PWR8-NEXT: xxswapd vs0, vs34 24; CHECK-PWR8-NEXT: mfvsrd r3, vs34 25; CHECK-PWR8-NEXT: cmpdi r3, 0 26; CHECK-PWR8-NEXT: li r3, 1 27; CHECK-PWR8-NEXT: mffprd r4, f0 28; CHECK-PWR8-NEXT: cmpldi cr1, r4, 35708 29; CHECK-PWR8-NEXT: crnand 4*cr5+lt, eq, 4*cr1+lt 30; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt 31; CHECK-PWR8-NEXT: blr 32; 33; CHECK-PWR7-LABEL: setcc_v1i128: 34; CHECK-PWR7: # %bb.0: # %entry 35; CHECK-PWR7-NEXT: li r5, 0 36; CHECK-PWR7-NEXT: cntlzd r3, r3 37; CHECK-PWR7-NEXT: ori r5, r5, 35708 38; CHECK-PWR7-NEXT: rldicl r3, r3, 58, 63 39; CHECK-PWR7-NEXT: subc r5, r4, r5 40; CHECK-PWR7-NEXT: subfe r4, r4, r4 41; CHECK-PWR7-NEXT: neg r4, r4 42; CHECK-PWR7-NEXT: and r3, r3, r4 43; CHECK-PWR7-NEXT: blr 44entry: 45 %0 = icmp ult <1 x i128> %a, <i128 35708> 46 %1 = zext <1 x i1> %0 to <1 x i64> 47 ret <1 x i64> %1 48} 49 50