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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
3; RUN:   -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
4; RUN:   -check-prefix=CHECK-LE %s
5; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
6; RUN:   -mtriple=powerpc64-linux-gnu < %s | FileCheck \
7; RUN:   -check-prefix=CHECK-BE %s
8; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
9; RUN:   -mtriple=powerpc-linux-gnu < %s | FileCheck \
10; RUN:   -check-prefix=CHECK-32 %s
11
12; Free probe
13define i8 @f0() #0 nounwind {
14; CHECK-LE-LABEL: f0:
15; CHECK-LE:       # %bb.0: # %entry
16; CHECK-LE-NEXT:    li r3, 3
17; CHECK-LE-NEXT:    stb r3, -64(r1)
18; CHECK-LE-NEXT:    lbz r3, -64(r1)
19; CHECK-LE-NEXT:    blr
20;
21; CHECK-BE-LABEL: f0:
22; CHECK-BE:       # %bb.0: # %entry
23; CHECK-BE-NEXT:    li r3, 3
24; CHECK-BE-NEXT:    stb r3, -64(r1)
25; CHECK-BE-NEXT:    lbz r3, -64(r1)
26; CHECK-BE-NEXT:    blr
27;
28; CHECK-32-LABEL: f0:
29; CHECK-32:       # %bb.0: # %entry
30; CHECK-32-NEXT:    stwu r1, -80(r1)
31; CHECK-32-NEXT:    li r3, 3
32; CHECK-32-NEXT:    stb r3, 16(r1)
33; CHECK-32-NEXT:    lbz r3, 16(r1)
34; CHECK-32-NEXT:    addi r1, r1, 80
35; CHECK-32-NEXT:    blr
36entry:
37  %a = alloca i8, i64 64
38  %b = getelementptr inbounds i8, i8* %a, i64 63
39  store volatile i8 3, i8* %a
40  %c = load volatile i8, i8* %a
41  ret i8 %c
42}
43
44define i8 @f1() #0 "stack-probe-size"="0" nounwind {
45; CHECK-LE-LABEL: f1:
46; CHECK-LE:       # %bb.0: # %entry
47; CHECK-LE-NEXT:    mr r12, r1
48; CHECK-LE-NEXT:    li r0, 259
49; CHECK-LE-NEXT:    mtctr r0
50; CHECK-LE-NEXT:  .LBB1_1: # %entry
51; CHECK-LE-NEXT:    #
52; CHECK-LE-NEXT:    stdu r12, -16(r1)
53; CHECK-LE-NEXT:    bdnz .LBB1_1
54; CHECK-LE-NEXT:  # %bb.2: # %entry
55; CHECK-LE-NEXT:    li r3, 3
56; CHECK-LE-NEXT:    stb r3, 48(r1)
57; CHECK-LE-NEXT:    lbz r3, 48(r1)
58; CHECK-LE-NEXT:    addi r1, r1, 4144
59; CHECK-LE-NEXT:    blr
60;
61; CHECK-BE-LABEL: f1:
62; CHECK-BE:       # %bb.0: # %entry
63; CHECK-BE-NEXT:    mr r12, r1
64; CHECK-BE-NEXT:    li r0, 260
65; CHECK-BE-NEXT:    mtctr r0
66; CHECK-BE-NEXT:  .LBB1_1: # %entry
67; CHECK-BE-NEXT:    #
68; CHECK-BE-NEXT:    stdu r12, -16(r1)
69; CHECK-BE-NEXT:    bdnz .LBB1_1
70; CHECK-BE-NEXT:  # %bb.2: # %entry
71; CHECK-BE-NEXT:    li r3, 3
72; CHECK-BE-NEXT:    stb r3, 64(r1)
73; CHECK-BE-NEXT:    lbz r3, 64(r1)
74; CHECK-BE-NEXT:    addi r1, r1, 4160
75; CHECK-BE-NEXT:    blr
76;
77; CHECK-32-LABEL: f1:
78; CHECK-32:       # %bb.0: # %entry
79; CHECK-32-NEXT:    mr r12, r1
80; CHECK-32-NEXT:    li r0, 257
81; CHECK-32-NEXT:    mtctr r0
82; CHECK-32-NEXT:  .LBB1_1: # %entry
83; CHECK-32-NEXT:    #
84; CHECK-32-NEXT:    stwu r12, -16(r1)
85; CHECK-32-NEXT:    bdnz .LBB1_1
86; CHECK-32-NEXT:  # %bb.2: # %entry
87; CHECK-32-NEXT:    li r3, 3
88; CHECK-32-NEXT:    sub r0, r1, r12
89; CHECK-32-NEXT:    stb r3, 16(r1)
90; CHECK-32-NEXT:    sub r0, r1, r0
91; CHECK-32-NEXT:    lbz r3, 16(r1)
92; CHECK-32-NEXT:    addi r1, r1, 4112
93; CHECK-32-NEXT:    blr
94entry:
95  %a = alloca i8, i64 4096
96  %b = getelementptr inbounds i8, i8* %a, i64 63
97  store volatile i8 3, i8* %a
98  %c = load volatile i8, i8* %a
99  ret i8 %c
100}
101
102define i8 @f2() #0 nounwind {
103; CHECK-LE-LABEL: f2:
104; CHECK-LE:       # %bb.0: # %entry
105; CHECK-LE-NEXT:    mr r12, r1
106; CHECK-LE-NEXT:    stdu r12, -48(r1)
107; CHECK-LE-NEXT:    li r0, 16
108; CHECK-LE-NEXT:    mtctr r0
109; CHECK-LE-NEXT:  .LBB2_1: # %entry
110; CHECK-LE-NEXT:    #
111; CHECK-LE-NEXT:    stdu r12, -4096(r1)
112; CHECK-LE-NEXT:    bdnz .LBB2_1
113; CHECK-LE-NEXT:  # %bb.2: # %entry
114; CHECK-LE-NEXT:    li r3, 3
115; CHECK-LE-NEXT:    stb r3, 48(r1)
116; CHECK-LE-NEXT:    lbz r3, 48(r1)
117; CHECK-LE-NEXT:    ld r1, 0(r1)
118; CHECK-LE-NEXT:    blr
119;
120; CHECK-BE-LABEL: f2:
121; CHECK-BE:       # %bb.0: # %entry
122; CHECK-BE-NEXT:    mr r12, r1
123; CHECK-BE-NEXT:    stdu r12, -64(r1)
124; CHECK-BE-NEXT:    li r0, 16
125; CHECK-BE-NEXT:    mtctr r0
126; CHECK-BE-NEXT:  .LBB2_1: # %entry
127; CHECK-BE-NEXT:    #
128; CHECK-BE-NEXT:    stdu r12, -4096(r1)
129; CHECK-BE-NEXT:    bdnz .LBB2_1
130; CHECK-BE-NEXT:  # %bb.2: # %entry
131; CHECK-BE-NEXT:    li r3, 3
132; CHECK-BE-NEXT:    stb r3, 64(r1)
133; CHECK-BE-NEXT:    lbz r3, 64(r1)
134; CHECK-BE-NEXT:    ld r1, 0(r1)
135; CHECK-BE-NEXT:    blr
136;
137; CHECK-32-LABEL: f2:
138; CHECK-32:       # %bb.0: # %entry
139; CHECK-32-NEXT:    mr r12, r1
140; CHECK-32-NEXT:    stwu r12, -16(r1)
141; CHECK-32-NEXT:    li r0, 16
142; CHECK-32-NEXT:    mtctr r0
143; CHECK-32-NEXT:  .LBB2_1: # %entry
144; CHECK-32-NEXT:    #
145; CHECK-32-NEXT:    stwu r12, -4096(r1)
146; CHECK-32-NEXT:    bdnz .LBB2_1
147; CHECK-32-NEXT:  # %bb.2: # %entry
148; CHECK-32-NEXT:    sub r0, r1, r12
149; CHECK-32-NEXT:    li r3, 3
150; CHECK-32-NEXT:    sub r0, r1, r0
151; CHECK-32-NEXT:    stb r3, 16(r1)
152; CHECK-32-NEXT:    mr r0, r31
153; CHECK-32-NEXT:    lbz r3, 16(r1)
154; CHECK-32-NEXT:    lwz r31, 0(r1)
155; CHECK-32-NEXT:    mr r1, r31
156; CHECK-32-NEXT:    mr r31, r0
157; CHECK-32-NEXT:    blr
158entry:
159  %a = alloca i8, i64 65536
160  %b = getelementptr inbounds i8, i8* %a, i64 63
161  store volatile i8 3, i8* %a
162  %c = load volatile i8, i8* %a
163  ret i8 %c
164}
165
166define i8 @f3() #0 "stack-probe-size"="32768" nounwind {
167; CHECK-LE-LABEL: f3:
168; CHECK-LE:       # %bb.0: # %entry
169; CHECK-LE-NEXT:    mr r12, r1
170; CHECK-LE-NEXT:    stdu r12, -48(r1)
171; CHECK-LE-NEXT:    stdu r12, -32768(r1)
172; CHECK-LE-NEXT:    stdu r12, -32768(r1)
173; CHECK-LE-NEXT:    li r3, 3
174; CHECK-LE-NEXT:    stb r3, 48(r1)
175; CHECK-LE-NEXT:    lbz r3, 48(r1)
176; CHECK-LE-NEXT:    ld r1, 0(r1)
177; CHECK-LE-NEXT:    blr
178;
179; CHECK-BE-LABEL: f3:
180; CHECK-BE:       # %bb.0: # %entry
181; CHECK-BE-NEXT:    mr r12, r1
182; CHECK-BE-NEXT:    stdu r12, -64(r1)
183; CHECK-BE-NEXT:    stdu r12, -32768(r1)
184; CHECK-BE-NEXT:    stdu r12, -32768(r1)
185; CHECK-BE-NEXT:    li r3, 3
186; CHECK-BE-NEXT:    stb r3, 64(r1)
187; CHECK-BE-NEXT:    lbz r3, 64(r1)
188; CHECK-BE-NEXT:    ld r1, 0(r1)
189; CHECK-BE-NEXT:    blr
190;
191; CHECK-32-LABEL: f3:
192; CHECK-32:       # %bb.0: # %entry
193; CHECK-32-NEXT:    mr r12, r1
194; CHECK-32-NEXT:    stwu r12, -16(r1)
195; CHECK-32-NEXT:    stwu r12, -32768(r1)
196; CHECK-32-NEXT:    stwu r12, -32768(r1)
197; CHECK-32-NEXT:    sub r0, r1, r12
198; CHECK-32-NEXT:    li r3, 3
199; CHECK-32-NEXT:    sub r0, r1, r0
200; CHECK-32-NEXT:    stb r3, 16(r1)
201; CHECK-32-NEXT:    mr r0, r31
202; CHECK-32-NEXT:    lbz r3, 16(r1)
203; CHECK-32-NEXT:    lwz r31, 0(r1)
204; CHECK-32-NEXT:    mr r1, r31
205; CHECK-32-NEXT:    mr r31, r0
206; CHECK-32-NEXT:    blr
207entry:
208  %a = alloca i8, i64 65536
209  %b = getelementptr inbounds i8, i8* %a, i64 63
210  store volatile i8 3, i8* %a
211  %c = load volatile i8, i8* %a
212  ret i8 %c
213}
214
215; Same as f2, but without protection.
216define i8 @f4() nounwind {
217; CHECK-LE-LABEL: f4:
218; CHECK-LE:       # %bb.0: # %entry
219; CHECK-LE-NEXT:    lis r0, -2
220; CHECK-LE-NEXT:    ori r0, r0, 65488
221; CHECK-LE-NEXT:    stdux r1, r1, r0
222; CHECK-LE-NEXT:    li r3, 3
223; CHECK-LE-NEXT:    stb r3, 48(r1)
224; CHECK-LE-NEXT:    lbz r3, 48(r1)
225; CHECK-LE-NEXT:    ld r1, 0(r1)
226; CHECK-LE-NEXT:    blr
227;
228; CHECK-BE-LABEL: f4:
229; CHECK-BE:       # %bb.0: # %entry
230; CHECK-BE-NEXT:    lis r0, -2
231; CHECK-BE-NEXT:    ori r0, r0, 65472
232; CHECK-BE-NEXT:    stdux r1, r1, r0
233; CHECK-BE-NEXT:    li r3, 3
234; CHECK-BE-NEXT:    stb r3, 64(r1)
235; CHECK-BE-NEXT:    lbz r3, 64(r1)
236; CHECK-BE-NEXT:    ld r1, 0(r1)
237; CHECK-BE-NEXT:    blr
238;
239; CHECK-32-LABEL: f4:
240; CHECK-32:       # %bb.0: # %entry
241; CHECK-32-NEXT:    lis r0, -2
242; CHECK-32-NEXT:    ori r0, r0, 65520
243; CHECK-32-NEXT:    stwux r1, r1, r0
244; CHECK-32-NEXT:    li r3, 3
245; CHECK-32-NEXT:    sub r0, r1, r0
246; CHECK-32-NEXT:    stb r3, 16(r1)
247; CHECK-32-NEXT:    mr r0, r31
248; CHECK-32-NEXT:    lbz r3, 16(r1)
249; CHECK-32-NEXT:    lwz r31, 0(r1)
250; CHECK-32-NEXT:    mr r1, r31
251; CHECK-32-NEXT:    mr r31, r0
252; CHECK-32-NEXT:    blr
253entry:
254  %a = alloca i8, i64 65536
255  %b = getelementptr inbounds i8, i8* %a, i64 63
256  store volatile i8 3, i8* %a
257  %c = load volatile i8, i8* %a
258  ret i8 %c
259}
260
261define i8 @f5() #0 "stack-probe-size"="65536" nounwind {
262; CHECK-LE-LABEL: f5:
263; CHECK-LE:       # %bb.0: # %entry
264; CHECK-LE-NEXT:    mr r12, r1
265; CHECK-LE-NEXT:    stdu r12, -48(r1)
266; CHECK-LE-NEXT:    li r0, 16
267; CHECK-LE-NEXT:    mtctr r0
268; CHECK-LE-NEXT:    lis r0, -1
269; CHECK-LE-NEXT:    nop
270; CHECK-LE-NEXT:  .LBB5_1: # %entry
271; CHECK-LE-NEXT:    #
272; CHECK-LE-NEXT:    stdux r12, r1, r0
273; CHECK-LE-NEXT:    bdnz .LBB5_1
274; CHECK-LE-NEXT:  # %bb.2: # %entry
275; CHECK-LE-NEXT:    li r3, 3
276; CHECK-LE-NEXT:    stb r3, 48(r1)
277; CHECK-LE-NEXT:    lbz r3, 48(r1)
278; CHECK-LE-NEXT:    ld r1, 0(r1)
279; CHECK-LE-NEXT:    blr
280;
281; CHECK-BE-LABEL: f5:
282; CHECK-BE:       # %bb.0: # %entry
283; CHECK-BE-NEXT:    mr r12, r1
284; CHECK-BE-NEXT:    stdu r12, -64(r1)
285; CHECK-BE-NEXT:    li r0, 16
286; CHECK-BE-NEXT:    mtctr r0
287; CHECK-BE-NEXT:    lis r0, -1
288; CHECK-BE-NEXT:    nop
289; CHECK-BE-NEXT:  .LBB5_1: # %entry
290; CHECK-BE-NEXT:    #
291; CHECK-BE-NEXT:    stdux r12, r1, r0
292; CHECK-BE-NEXT:    bdnz .LBB5_1
293; CHECK-BE-NEXT:  # %bb.2: # %entry
294; CHECK-BE-NEXT:    li r3, 3
295; CHECK-BE-NEXT:    stb r3, 64(r1)
296; CHECK-BE-NEXT:    lbz r3, 64(r1)
297; CHECK-BE-NEXT:    ld r1, 0(r1)
298; CHECK-BE-NEXT:    blr
299;
300; CHECK-32-LABEL: f5:
301; CHECK-32:       # %bb.0: # %entry
302; CHECK-32-NEXT:    mr r12, r1
303; CHECK-32-NEXT:    stwu r12, -16(r1)
304; CHECK-32-NEXT:    li r0, 16
305; CHECK-32-NEXT:    mtctr r0
306; CHECK-32-NEXT:    lis r0, -1
307; CHECK-32-NEXT:    nop
308; CHECK-32-NEXT:  .LBB5_1: # %entry
309; CHECK-32-NEXT:    #
310; CHECK-32-NEXT:    stwux r12, r1, r0
311; CHECK-32-NEXT:    bdnz .LBB5_1
312; CHECK-32-NEXT:  # %bb.2: # %entry
313; CHECK-32-NEXT:    sub r0, r1, r12
314; CHECK-32-NEXT:    li r3, 3
315; CHECK-32-NEXT:    sub r0, r1, r0
316; CHECK-32-NEXT:    stb r3, 16(r1)
317; CHECK-32-NEXT:    mr r0, r31
318; CHECK-32-NEXT:    lbz r3, 16(r1)
319; CHECK-32-NEXT:    lwz r31, 0(r1)
320; CHECK-32-NEXT:    mr r1, r31
321; CHECK-32-NEXT:    mr r31, r0
322; CHECK-32-NEXT:    blr
323entry:
324  %a = alloca i8, i64 1048576
325  %b = getelementptr inbounds i8, i8* %a, i64 63
326  store volatile i8 3, i8* %a
327  %c = load volatile i8, i8* %a
328  ret i8 %c
329}
330
331define i8 @f6() #0 nounwind {
332; CHECK-LE-LABEL: f6:
333; CHECK-LE:       # %bb.0: # %entry
334; CHECK-LE-NEXT:    mr r12, r1
335; CHECK-LE-NEXT:    stdu r12, -48(r1)
336; CHECK-LE-NEXT:    lis r0, 4
337; CHECK-LE-NEXT:    nop
338; CHECK-LE-NEXT:    mtctr r0
339; CHECK-LE-NEXT:  .LBB6_1: # %entry
340; CHECK-LE-NEXT:    #
341; CHECK-LE-NEXT:    stdu r12, -4096(r1)
342; CHECK-LE-NEXT:    bdnz .LBB6_1
343; CHECK-LE-NEXT:  # %bb.2: # %entry
344; CHECK-LE-NEXT:    li r3, 3
345; CHECK-LE-NEXT:    stb r3, 48(r1)
346; CHECK-LE-NEXT:    lbz r3, 48(r1)
347; CHECK-LE-NEXT:    ld r1, 0(r1)
348; CHECK-LE-NEXT:    blr
349;
350; CHECK-BE-LABEL: f6:
351; CHECK-BE:       # %bb.0: # %entry
352; CHECK-BE-NEXT:    mr r12, r1
353; CHECK-BE-NEXT:    stdu r12, -64(r1)
354; CHECK-BE-NEXT:    lis r0, 4
355; CHECK-BE-NEXT:    nop
356; CHECK-BE-NEXT:    mtctr r0
357; CHECK-BE-NEXT:  .LBB6_1: # %entry
358; CHECK-BE-NEXT:    #
359; CHECK-BE-NEXT:    stdu r12, -4096(r1)
360; CHECK-BE-NEXT:    bdnz .LBB6_1
361; CHECK-BE-NEXT:  # %bb.2: # %entry
362; CHECK-BE-NEXT:    li r3, 3
363; CHECK-BE-NEXT:    stb r3, 64(r1)
364; CHECK-BE-NEXT:    lbz r3, 64(r1)
365; CHECK-BE-NEXT:    ld r1, 0(r1)
366; CHECK-BE-NEXT:    blr
367;
368; CHECK-32-LABEL: f6:
369; CHECK-32:       # %bb.0: # %entry
370; CHECK-32-NEXT:    mr r12, r1
371; CHECK-32-NEXT:    stwu r12, -16(r1)
372; CHECK-32-NEXT:    lis r0, 4
373; CHECK-32-NEXT:    nop
374; CHECK-32-NEXT:    mtctr r0
375; CHECK-32-NEXT:  .LBB6_1: # %entry
376; CHECK-32-NEXT:    #
377; CHECK-32-NEXT:    stwu r12, -4096(r1)
378; CHECK-32-NEXT:    bdnz .LBB6_1
379; CHECK-32-NEXT:  # %bb.2: # %entry
380; CHECK-32-NEXT:    sub r0, r1, r12
381; CHECK-32-NEXT:    li r3, 3
382; CHECK-32-NEXT:    sub r0, r1, r0
383; CHECK-32-NEXT:    stb r3, 16(r1)
384; CHECK-32-NEXT:    mr r0, r31
385; CHECK-32-NEXT:    lbz r3, 16(r1)
386; CHECK-32-NEXT:    lwz r31, 0(r1)
387; CHECK-32-NEXT:    mr r1, r31
388; CHECK-32-NEXT:    mr r31, r0
389; CHECK-32-NEXT:    blr
390entry:
391  %a = alloca i8, i64 1073741824
392  %b = getelementptr inbounds i8, i8* %a, i64 63
393  store volatile i8 3, i8* %a
394  %c = load volatile i8, i8* %a
395  ret i8 %c
396}
397
398define i8 @f7() #0 "stack-probe-size"="65536" nounwind {
399; CHECK-LE-LABEL: f7:
400; CHECK-LE:       # %bb.0: # %entry
401; CHECK-LE-NEXT:    lis r0, -1
402; CHECK-LE-NEXT:    mr r12, r1
403; CHECK-LE-NEXT:    ori r0, r0, 13776
404; CHECK-LE-NEXT:    stdux r12, r1, r0
405; CHECK-LE-NEXT:    li r0, 15258
406; CHECK-LE-NEXT:    mtctr r0
407; CHECK-LE-NEXT:    lis r0, -1
408; CHECK-LE-NEXT:    nop
409; CHECK-LE-NEXT:  .LBB7_1: # %entry
410; CHECK-LE-NEXT:    #
411; CHECK-LE-NEXT:    stdux r12, r1, r0
412; CHECK-LE-NEXT:    bdnz .LBB7_1
413; CHECK-LE-NEXT:  # %bb.2: # %entry
414; CHECK-LE-NEXT:    li r3, 3
415; CHECK-LE-NEXT:    stb r3, 41(r1)
416; CHECK-LE-NEXT:    lbz r3, 41(r1)
417; CHECK-LE-NEXT:    ld r1, 0(r1)
418; CHECK-LE-NEXT:    blr
419;
420; CHECK-BE-LABEL: f7:
421; CHECK-BE:       # %bb.0: # %entry
422; CHECK-BE-NEXT:    lis r0, -1
423; CHECK-BE-NEXT:    mr r12, r1
424; CHECK-BE-NEXT:    ori r0, r0, 13760
425; CHECK-BE-NEXT:    stdux r12, r1, r0
426; CHECK-BE-NEXT:    li r0, 15258
427; CHECK-BE-NEXT:    mtctr r0
428; CHECK-BE-NEXT:    lis r0, -1
429; CHECK-BE-NEXT:    nop
430; CHECK-BE-NEXT:  .LBB7_1: # %entry
431; CHECK-BE-NEXT:    #
432; CHECK-BE-NEXT:    stdux r12, r1, r0
433; CHECK-BE-NEXT:    bdnz .LBB7_1
434; CHECK-BE-NEXT:  # %bb.2: # %entry
435; CHECK-BE-NEXT:    li r3, 3
436; CHECK-BE-NEXT:    stb r3, 57(r1)
437; CHECK-BE-NEXT:    lbz r3, 57(r1)
438; CHECK-BE-NEXT:    ld r1, 0(r1)
439; CHECK-BE-NEXT:    blr
440;
441; CHECK-32-LABEL: f7:
442; CHECK-32:       # %bb.0: # %entry
443; CHECK-32-NEXT:    lis r0, -1
444; CHECK-32-NEXT:    mr r12, r1
445; CHECK-32-NEXT:    ori r0, r0, 13808
446; CHECK-32-NEXT:    stwux r12, r1, r0
447; CHECK-32-NEXT:    li r0, 15258
448; CHECK-32-NEXT:    mtctr r0
449; CHECK-32-NEXT:    lis r0, -1
450; CHECK-32-NEXT:    nop
451; CHECK-32-NEXT:  .LBB7_1: # %entry
452; CHECK-32-NEXT:    #
453; CHECK-32-NEXT:    stwux r12, r1, r0
454; CHECK-32-NEXT:    bdnz .LBB7_1
455; CHECK-32-NEXT:  # %bb.2: # %entry
456; CHECK-32-NEXT:    sub r0, r1, r12
457; CHECK-32-NEXT:    li r3, 3
458; CHECK-32-NEXT:    sub r0, r1, r0
459; CHECK-32-NEXT:    stb r3, 9(r1)
460; CHECK-32-NEXT:    mr r0, r31
461; CHECK-32-NEXT:    lbz r3, 9(r1)
462; CHECK-32-NEXT:    lwz r31, 0(r1)
463; CHECK-32-NEXT:    mr r1, r31
464; CHECK-32-NEXT:    mr r31, r0
465; CHECK-32-NEXT:    blr
466entry:
467  %a = alloca i8, i64 1000000007
468  %b = getelementptr inbounds i8, i8* %a, i64 101
469  store volatile i8 3, i8* %a
470  %c = load volatile i8, i8* %a
471  ret i8 %c
472}
473
474attributes #0 = { "probe-stack"="inline-asm" }
475