1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8@glob = local_unnamed_addr global i64 0, align 8 9 10define signext i32 @test_ilesll(i64 %a, i64 %b) { 11; CHECK-LABEL: test_ilesll: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: sradi r5, r4, 63 14; CHECK-NEXT: rldicl r6, r3, 1, 63 15; CHECK-NEXT: subfc r3, r3, r4 16; CHECK-NEXT: adde r3, r5, r6 17; CHECK-NEXT: blr 18; CHECK-BE-LABEL: test_ilesll: 19; CHECK-BE: # %bb.0: # %entry 20; CHECK-BE-NEXT: sradi r5, r4, 63 21; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 22; CHECK-BE-NEXT: subc r3, r4, r3 23; CHECK-BE-NEXT: adde r3, r5, r6 24; CHECK-BE-NEXT: blr 25; 26; CHECK-LE-LABEL: test_ilesll: 27; CHECK-LE: # %bb.0: # %entry 28; CHECK-LE-NEXT: sradi r5, r4, 63 29; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 30; CHECK-LE-NEXT: subc r3, r4, r3 31; CHECK-LE-NEXT: adde r3, r5, r6 32; CHECK-LE-NEXT: blr 33entry: 34 %cmp = icmp sle i64 %a, %b 35 %conv = zext i1 %cmp to i32 36 ret i32 %conv 37} 38 39define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { 40; CHECK-LABEL: test_ilesll_sext: 41; CHECK: # %bb.0: # %entry 42; CHECK-NEXT: sradi r5, r4, 63 43; CHECK-NEXT: rldicl r6, r3, 1, 63 44; CHECK-NEXT: subfc r3, r3, r4 45; CHECK-NEXT: adde r3, r5, r6 46; CHECK-NEXT: neg r3, r3 47; CHECK-NEXT: blr 48; CHECK-BE-LABEL: test_ilesll_sext: 49; CHECK-BE: # %bb.0: # %entry 50; CHECK-BE-NEXT: sradi r5, r4, 63 51; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 52; CHECK-BE-NEXT: subc r3, r4, r3 53; CHECK-BE-NEXT: adde r3, r5, r6 54; CHECK-BE-NEXT: neg r3, r3 55; CHECK-BE-NEXT: blr 56; 57; CHECK-LE-LABEL: test_ilesll_sext: 58; CHECK-LE: # %bb.0: # %entry 59; CHECK-LE-NEXT: sradi r5, r4, 63 60; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 61; CHECK-LE-NEXT: subc r3, r4, r3 62; CHECK-LE-NEXT: adde r3, r5, r6 63; CHECK-LE-NEXT: neg r3, r3 64; CHECK-LE-NEXT: blr 65entry: 66 %cmp = icmp sle i64 %a, %b 67 %sub = sext i1 %cmp to i32 68 ret i32 %sub 69} 70 71define signext i32 @test_ilesll_z(i64 %a) { 72; CHECK-LABEL: test_ilesll_z: 73; CHECK: # %bb.0: # %entry 74; CHECK-NEXT: addi r4, r3, -1 75; CHECK-NEXT: or r3, r4, r3 76; CHECK-NEXT: rldicl r3, r3, 1, 63 77; CHECK-NEXT: blr 78; CHECK-BE-LABEL: test_ilesll_z: 79; CHECK-BE: # %bb.0: # %entry 80; CHECK-BE-NEXT: addi r4, r3, -1 81; CHECK-BE-NEXT: or r3, r4, r3 82; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 83; CHECK-BE-NEXT: blr 84; 85; CHECK-LE-LABEL: test_ilesll_z: 86; CHECK-LE: # %bb.0: # %entry 87; CHECK-LE-NEXT: addi r4, r3, -1 88; CHECK-LE-NEXT: or r3, r4, r3 89; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 90; CHECK-LE-NEXT: blr 91entry: 92 %cmp = icmp slt i64 %a, 1 93 %conv = zext i1 %cmp to i32 94 ret i32 %conv 95} 96 97define signext i32 @test_ilesll_sext_z(i64 %a) { 98; CHECK-LABEL: test_ilesll_sext_z: 99; CHECK: # %bb.0: # %entry 100; CHECK-NEXT: addi r4, r3, -1 101; CHECK-NEXT: or r3, r4, r3 102; CHECK-NEXT: sradi r3, r3, 63 103; CHECK-NEXT: blr 104; CHECK-BE-LABEL: test_ilesll_sext_z: 105; CHECK-BE: # %bb.0: # %entry 106; CHECK-BE-NEXT: addi r4, r3, -1 107; CHECK-BE-NEXT: or r3, r4, r3 108; CHECK-BE-NEXT: sradi r3, r3, 63 109; CHECK-BE-NEXT: blr 110; 111; CHECK-LE-LABEL: test_ilesll_sext_z: 112; CHECK-LE: # %bb.0: # %entry 113; CHECK-LE-NEXT: addi r4, r3, -1 114; CHECK-LE-NEXT: or r3, r4, r3 115; CHECK-LE-NEXT: sradi r3, r3, 63 116; CHECK-LE-NEXT: blr 117entry: 118 %cmp = icmp slt i64 %a, 1 119 %sub = sext i1 %cmp to i32 120 ret i32 %sub 121} 122 123define void @test_ilesll_store(i64 %a, i64 %b) { 124; CHECK-LABEL: test_ilesll_store: 125; CHECK: # %bb.0: # %entry 126; CHECK-NEXT: sradi r6, r4, 63 127; CHECK-NEXT: addis r5, r2, glob@toc@ha 128; CHECK-NEXT: subfc r4, r3, r4 129; CHECK-NEXT: rldicl r3, r3, 1, 63 130; CHECK-NEXT: adde r3, r6, r3 131; CHECK-NEXT: std r3, glob@toc@l(r5) 132; CHECK-NEXT: blr 133; CHECK-BE-LABEL: test_ilesll_store: 134; CHECK-BE: # %bb.0: # %entry 135; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha 136; CHECK-BE-NEXT: sradi r6, r4, 63 137; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) 138; CHECK-BE-NEXT: subc r4, r4, r3 139; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 140; CHECK-BE-NEXT: adde r3, r6, r3 141; CHECK-BE-NEXT: std r3, 0(r5) 142; CHECK-BE-NEXT: blr 143; 144; CHECK-LE-LABEL: test_ilesll_store: 145; CHECK-LE: # %bb.0: # %entry 146; CHECK-LE-NEXT: sradi r6, r4, 63 147; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha 148; CHECK-LE-NEXT: subc r4, r4, r3 149; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 150; CHECK-LE-NEXT: adde r3, r6, r3 151; CHECK-LE-NEXT: std r3, glob@toc@l(r5) 152; CHECK-LE-NEXT: blr 153entry: 154 %cmp = icmp sle i64 %a, %b 155 %conv1 = zext i1 %cmp to i64 156 store i64 %conv1, i64* @glob, align 8 157 ret void 158} 159 160define void @test_ilesll_sext_store(i64 %a, i64 %b) { 161; CHECK-LABEL: test_ilesll_sext_store: 162; CHECK: # %bb.0: # %entry 163; CHECK-NEXT: sradi r6, r4, 63 164; CHECK-NEXT: addis r5, r2, glob@toc@ha 165; CHECK-NEXT: subfc r4, r3, r4 166; CHECK-NEXT: rldicl r3, r3, 1, 63 167; CHECK-NEXT: adde r3, r6, r3 168; CHECK-NEXT: neg r3, r3 169; CHECK-NEXT: std r3, glob@toc@l(r5) 170; CHECK-NEXT: blr 171; CHECK-BE-LABEL: test_ilesll_sext_store: 172; CHECK-BE: # %bb.0: # %entry 173; CHECK-BE-NEXT: sradi r6, r4, 63 174; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha 175; CHECK-BE-NEXT: subc r4, r4, r3 176; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 177; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) 178; CHECK-BE-NEXT: adde r3, r6, r3 179; CHECK-BE-NEXT: neg r3, r3 180; CHECK-BE-NEXT: std r3, 0(r4) 181; CHECK-BE-NEXT: blr 182; 183; CHECK-LE-LABEL: test_ilesll_sext_store: 184; CHECK-LE: # %bb.0: # %entry 185; CHECK-LE-NEXT: sradi r6, r4, 63 186; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha 187; CHECK-LE-NEXT: subc r4, r4, r3 188; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 189; CHECK-LE-NEXT: adde r3, r6, r3 190; CHECK-LE-NEXT: neg r3, r3 191; CHECK-LE-NEXT: std r3, glob@toc@l(r5) 192; CHECK-LE-NEXT: blr 193entry: 194 %cmp = icmp sle i64 %a, %b 195 %conv1 = sext i1 %cmp to i64 196 store i64 %conv1, i64* @glob, align 8 197 ret void 198} 199 200define void @test_ilesll_z_store(i64 %a) { 201; CHECK-LABEL: test_ilesll_z_store: 202; CHECK: # %bb.0: # %entry 203; CHECK-NEXT: addi r5, r3, -1 204; CHECK-NEXT: addis r4, r2, glob@toc@ha 205; CHECK-NEXT: or r3, r5, r3 206; CHECK-NEXT: rldicl r3, r3, 1, 63 207; CHECK-NEXT: std r3, glob@toc@l(r4) 208; CHECK-NEXT: blr 209; CHECK-BE-LABEL: test_ilesll_z_store: 210; CHECK-BE: # %bb.0: # %entry 211; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 212; CHECK-BE-NEXT: addi r5, r3, -1 213; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 214; CHECK-BE-NEXT: or r3, r5, r3 215; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 216; CHECK-BE-NEXT: std r3, 0(r4) 217; CHECK-BE-NEXT: blr 218; 219; CHECK-LE-LABEL: test_ilesll_z_store: 220; CHECK-LE: # %bb.0: # %entry 221; CHECK-LE-NEXT: addi r5, r3, -1 222; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha 223; CHECK-LE-NEXT: or r3, r5, r3 224; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 225; CHECK-LE-NEXT: std r3, glob@toc@l(r4) 226; CHECK-LE-NEXT: blr 227entry: 228 %cmp = icmp slt i64 %a, 1 229 %conv1 = zext i1 %cmp to i64 230 store i64 %conv1, i64* @glob, align 8 231 ret void 232} 233 234define void @test_ilesll_sext_z_store(i64 %a) { 235; CHECK-LABEL: test_ilesll_sext_z_store: 236; CHECK: # %bb.0: # %entry 237; CHECK-NEXT: addi r5, r3, -1 238; CHECK-NEXT: addis r4, r2, glob@toc@ha 239; CHECK-NEXT: or r3, r5, r3 240; CHECK-NEXT: sradi r3, r3, 63 241; CHECK-NEXT: std r3, glob@toc@l(r4) 242; CHECK-NEXT: blr 243; CHECK-BE-LABEL: test_ilesll_sext_z_store: 244; CHECK-BE: # %bb.0: # %entry 245; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha 246; CHECK-BE-NEXT: addi r5, r3, -1 247; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) 248; CHECK-BE-NEXT: or r3, r5, r3 249; CHECK-BE-NEXT: sradi r3, r3, 63 250; CHECK-BE-NEXT: std r3, 0(r4) 251; CHECK-BE-NEXT: blr 252; 253; CHECK-LE-LABEL: test_ilesll_sext_z_store: 254; CHECK-LE: # %bb.0: # %entry 255; CHECK-LE-NEXT: addi r5, r3, -1 256; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha 257; CHECK-LE-NEXT: or r3, r5, r3 258; CHECK-LE-NEXT: sradi r3, r3, 63 259; CHECK-LE-NEXT: std r3, glob@toc@l(r4) 260; CHECK-LE-NEXT: blr 261entry: 262 %cmp = icmp slt i64 %a, 1 263 %conv1 = sext i1 %cmp to i64 264 store i64 %conv1, i64* @glob, align 8 265 ret void 266} 267