1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 9@glob = local_unnamed_addr global i32 0, align 4 10 11; Function Attrs: norecurse nounwind readnone 12define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) { 13; CHECK-LABEL: test_llltui: 14; CHECK: # %bb.0: # %entry 15; CHECK-NEXT: sub r3, r3, r4 16; CHECK-NEXT: rldicl r3, r3, 1, 63 17; CHECK-NEXT: blr 18entry: 19 %cmp = icmp ult i32 %a, %b 20 %conv1 = zext i1 %cmp to i64 21 ret i64 %conv1 22} 23 24; Function Attrs: norecurse nounwind readnone 25define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) { 26; CHECK-LABEL: test_llltui_sext: 27; CHECK: # %bb.0: # %entry 28; CHECK-NEXT: sub r3, r3, r4 29; CHECK-NEXT: sradi r3, r3, 63 30; CHECK-NEXT: blr 31entry: 32 %cmp = icmp ult i32 %a, %b 33 %conv1 = sext i1 %cmp to i64 34 ret i64 %conv1 35} 36 37; Function Attrs: norecurse nounwind readnone 38define i64 @test_llltui_z(i32 zeroext %a) { 39; CHECK-LABEL: test_llltui_z: 40; CHECK: # %bb.0: # %entry 41; CHECK-NEXT: li r3, 0 42; CHECK-NEXT: blr 43entry: 44 ret i64 0 45} 46 47; Function Attrs: norecurse nounwind readnone 48define i64 @test_llltui_sext_z(i32 zeroext %a) { 49; CHECK-LABEL: test_llltui_sext_z: 50; CHECK: # %bb.0: # %entry 51; CHECK-NEXT: li r3, 0 52; CHECK-NEXT: blr 53entry: 54 ret i64 0 55} 56 57; Function Attrs: norecurse nounwind 58define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) { 59; CHECK-LABEL: test_llltui_store: 60; CHECK: # %bb.0: # %entry 61; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 62; CHECK-NEXT: sub r3, r3, r4 63; CHECK-NEXT: ld r5, .LC0@toc@l(r5) 64; CHECK-NEXT: rldicl r3, r3, 1, 63 65; CHECK-NEXT: stw r3, 0(r5) 66; CHECK-NEXT: blr 67entry: 68 %cmp = icmp ult i32 %a, %b 69 %conv = zext i1 %cmp to i32 70 store i32 %conv, i32* @glob, align 4 71 ret void 72} 73 74; Function Attrs: norecurse nounwind 75define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) { 76; CHECK-LABEL: test_llltui_sext_store: 77; CHECK: # %bb.0: # %entry 78; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 79; CHECK-NEXT: sub r3, r3, r4 80; CHECK-NEXT: ld r5, .LC0@toc@l(r5) 81; CHECK-NEXT: sradi r3, r3, 63 82; CHECK-NEXT: stw r3, 0(r5) 83; CHECK-NEXT: blr 84entry: 85 %cmp = icmp ult i32 %a, %b 86 %sub = sext i1 %cmp to i32 87 store i32 %sub, i32* @glob, align 4 88 ret void 89} 90 91; Function Attrs: norecurse nounwind 92define void @test_llltui_z_store(i32 zeroext %a) { 93; CHECK-LABEL: test_llltui_z_store: 94; CHECK: # %bb.0: # %entry 95; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 96; CHECK-NEXT: li r4, 0 97; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 98; CHECK-NEXT: stw r4, 0(r3) 99; CHECK-NEXT: blr 100entry: 101 store i32 0, i32* @glob, align 4 102 ret void 103} 104 105; Function Attrs: norecurse nounwind 106define void @test_llltui_sext_z_store(i32 zeroext %a) { 107; CHECK-LABEL: test_llltui_sext_z_store: 108; CHECK: # %bb.0: # %entry 109; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 110; CHECK-NEXT: li r4, 0 111; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 112; CHECK-NEXT: stw r4, 0(r3) 113; CHECK-NEXT: blr 114entry: 115 store i32 0, i32* @glob, align 4 116 ret void 117} 118 119