1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs < %s | FileCheck %s 3target datalayout = "E-m:e-i64:64-n32:64" 4target triple = "powerpc64-unknown-linux-gnu" 5 6define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 { 7; CHECK-LABEL: test_l_v16i8: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: li 4, 15 10; CHECK-NEXT: lvsl 3, 0, 3 11; CHECK-NEXT: lvx 2, 3, 4 12; CHECK-NEXT: lvx 4, 0, 3 13; CHECK-NEXT: vperm 2, 4, 2, 3 14; CHECK-NEXT: blr 15entry: 16 %r = load <16 x i8>, <16 x i8>* %p, align 1 17 ret <16 x i8> %r 18 19} 20 21define <32 x i8> @test_l_v32i8(<32 x i8>* %p) #0 { 22; CHECK-LABEL: test_l_v32i8: 23; CHECK: # %bb.0: # %entry 24; CHECK-NEXT: li 4, 31 25; CHECK-NEXT: lvsl 5, 0, 3 26; CHECK-NEXT: lvx 2, 3, 4 27; CHECK-NEXT: li 4, 16 28; CHECK-NEXT: lvx 4, 3, 4 29; CHECK-NEXT: lvx 0, 0, 3 30; CHECK-NEXT: vperm 3, 4, 2, 5 31; CHECK-NEXT: vperm 2, 0, 4, 5 32; CHECK-NEXT: blr 33entry: 34 %r = load <32 x i8>, <32 x i8>* %p, align 1 35 ret <32 x i8> %r 36 37} 38 39define <8 x i16> @test_l_v8i16(<8 x i16>* %p) #0 { 40; CHECK-LABEL: test_l_v8i16: 41; CHECK: # %bb.0: # %entry 42; CHECK-NEXT: li 4, 15 43; CHECK-NEXT: lvsl 3, 0, 3 44; CHECK-NEXT: lvx 2, 3, 4 45; CHECK-NEXT: lvx 4, 0, 3 46; CHECK-NEXT: vperm 2, 4, 2, 3 47; CHECK-NEXT: blr 48entry: 49 %r = load <8 x i16>, <8 x i16>* %p, align 2 50 ret <8 x i16> %r 51 52} 53 54define <16 x i16> @test_l_v16i16(<16 x i16>* %p) #0 { 55; CHECK-LABEL: test_l_v16i16: 56; CHECK: # %bb.0: # %entry 57; CHECK-NEXT: li 4, 31 58; CHECK-NEXT: lvsl 5, 0, 3 59; CHECK-NEXT: lvx 2, 3, 4 60; CHECK-NEXT: li 4, 16 61; CHECK-NEXT: lvx 4, 3, 4 62; CHECK-NEXT: lvx 0, 0, 3 63; CHECK-NEXT: vperm 3, 4, 2, 5 64; CHECK-NEXT: vperm 2, 0, 4, 5 65; CHECK-NEXT: blr 66entry: 67 %r = load <16 x i16>, <16 x i16>* %p, align 2 68 ret <16 x i16> %r 69 70} 71 72define <4 x i32> @test_l_v4i32(<4 x i32>* %p) #0 { 73; CHECK-LABEL: test_l_v4i32: 74; CHECK: # %bb.0: # %entry 75; CHECK-NEXT: li 4, 15 76; CHECK-NEXT: lvsl 3, 0, 3 77; CHECK-NEXT: lvx 2, 3, 4 78; CHECK-NEXT: lvx 4, 0, 3 79; CHECK-NEXT: vperm 2, 4, 2, 3 80; CHECK-NEXT: blr 81entry: 82 %r = load <4 x i32>, <4 x i32>* %p, align 4 83 ret <4 x i32> %r 84 85} 86 87define <8 x i32> @test_l_v8i32(<8 x i32>* %p) #0 { 88; CHECK-LABEL: test_l_v8i32: 89; CHECK: # %bb.0: # %entry 90; CHECK-NEXT: li 4, 31 91; CHECK-NEXT: lvsl 5, 0, 3 92; CHECK-NEXT: lvx 2, 3, 4 93; CHECK-NEXT: li 4, 16 94; CHECK-NEXT: lvx 4, 3, 4 95; CHECK-NEXT: lvx 0, 0, 3 96; CHECK-NEXT: vperm 3, 4, 2, 5 97; CHECK-NEXT: vperm 2, 0, 4, 5 98; CHECK-NEXT: blr 99entry: 100 %r = load <8 x i32>, <8 x i32>* %p, align 4 101 ret <8 x i32> %r 102 103} 104 105define <2 x i64> @test_l_v2i64(<2 x i64>* %p) #0 { 106; CHECK-LABEL: test_l_v2i64: 107; CHECK: # %bb.0: # %entry 108; CHECK-NEXT: lxvd2x 34, 0, 3 109; CHECK-NEXT: blr 110entry: 111 %r = load <2 x i64>, <2 x i64>* %p, align 8 112 ret <2 x i64> %r 113 114} 115 116define <4 x i64> @test_l_v4i64(<4 x i64>* %p) #0 { 117; CHECK-LABEL: test_l_v4i64: 118; CHECK: # %bb.0: # %entry 119; CHECK-NEXT: li 4, 16 120; CHECK-NEXT: lxvd2x 34, 0, 3 121; CHECK-NEXT: lxvd2x 35, 3, 4 122; CHECK-NEXT: blr 123entry: 124 %r = load <4 x i64>, <4 x i64>* %p, align 8 125 ret <4 x i64> %r 126 127} 128 129define <4 x float> @test_l_v4float(<4 x float>* %p) #0 { 130; CHECK-LABEL: test_l_v4float: 131; CHECK: # %bb.0: # %entry 132; CHECK-NEXT: li 4, 15 133; CHECK-NEXT: lvsl 3, 0, 3 134; CHECK-NEXT: lvx 2, 3, 4 135; CHECK-NEXT: lvx 4, 0, 3 136; CHECK-NEXT: vperm 2, 4, 2, 3 137; CHECK-NEXT: blr 138entry: 139 %r = load <4 x float>, <4 x float>* %p, align 4 140 ret <4 x float> %r 141 142} 143 144define <8 x float> @test_l_v8float(<8 x float>* %p) #0 { 145; CHECK-LABEL: test_l_v8float: 146; CHECK: # %bb.0: # %entry 147; CHECK-NEXT: li 4, 31 148; CHECK-NEXT: lvsl 5, 0, 3 149; CHECK-NEXT: lvx 2, 3, 4 150; CHECK-NEXT: li 4, 16 151; CHECK-NEXT: lvx 4, 3, 4 152; CHECK-NEXT: lvx 0, 0, 3 153; CHECK-NEXT: vperm 3, 4, 2, 5 154; CHECK-NEXT: vperm 2, 0, 4, 5 155; CHECK-NEXT: blr 156entry: 157 %r = load <8 x float>, <8 x float>* %p, align 4 158 ret <8 x float> %r 159 160} 161 162define <2 x double> @test_l_v2double(<2 x double>* %p) #0 { 163; CHECK-LABEL: test_l_v2double: 164; CHECK: # %bb.0: # %entry 165; CHECK-NEXT: lxvd2x 34, 0, 3 166; CHECK-NEXT: blr 167entry: 168 %r = load <2 x double>, <2 x double>* %p, align 8 169 ret <2 x double> %r 170 171} 172 173define <4 x double> @test_l_v4double(<4 x double>* %p) #0 { 174; CHECK-LABEL: test_l_v4double: 175; CHECK: # %bb.0: # %entry 176; CHECK-NEXT: li 4, 16 177; CHECK-NEXT: lxvd2x 34, 0, 3 178; CHECK-NEXT: lxvd2x 35, 3, 4 179; CHECK-NEXT: blr 180entry: 181 %r = load <4 x double>, <4 x double>* %p, align 8 182 ret <4 x double> %r 183 184} 185 186define <16 x i8> @test_l_p8v16i8(<16 x i8>* %p) #2 { 187; CHECK-LABEL: test_l_p8v16i8: 188; CHECK: # %bb.0: # %entry 189; CHECK-NEXT: lxvw4x 34, 0, 3 190; CHECK-NEXT: blr 191entry: 192 %r = load <16 x i8>, <16 x i8>* %p, align 1 193 ret <16 x i8> %r 194 195} 196 197define <32 x i8> @test_l_p8v32i8(<32 x i8>* %p) #2 { 198; CHECK-LABEL: test_l_p8v32i8: 199; CHECK: # %bb.0: # %entry 200; CHECK-NEXT: li 4, 16 201; CHECK-NEXT: lxvw4x 34, 0, 3 202; CHECK-NEXT: lxvw4x 35, 3, 4 203; CHECK-NEXT: blr 204entry: 205 %r = load <32 x i8>, <32 x i8>* %p, align 1 206 ret <32 x i8> %r 207 208} 209 210define <8 x i16> @test_l_p8v8i16(<8 x i16>* %p) #2 { 211; CHECK-LABEL: test_l_p8v8i16: 212; CHECK: # %bb.0: # %entry 213; CHECK-NEXT: lxvw4x 34, 0, 3 214; CHECK-NEXT: blr 215entry: 216 %r = load <8 x i16>, <8 x i16>* %p, align 2 217 ret <8 x i16> %r 218 219} 220 221define <16 x i16> @test_l_p8v16i16(<16 x i16>* %p) #2 { 222; CHECK-LABEL: test_l_p8v16i16: 223; CHECK: # %bb.0: # %entry 224; CHECK-NEXT: li 4, 16 225; CHECK-NEXT: lxvw4x 34, 0, 3 226; CHECK-NEXT: lxvw4x 35, 3, 4 227; CHECK-NEXT: blr 228entry: 229 %r = load <16 x i16>, <16 x i16>* %p, align 2 230 ret <16 x i16> %r 231 232} 233 234define <4 x i32> @test_l_p8v4i32(<4 x i32>* %p) #2 { 235; CHECK-LABEL: test_l_p8v4i32: 236; CHECK: # %bb.0: # %entry 237; CHECK-NEXT: lxvw4x 34, 0, 3 238; CHECK-NEXT: blr 239entry: 240 %r = load <4 x i32>, <4 x i32>* %p, align 4 241 ret <4 x i32> %r 242 243} 244 245define <8 x i32> @test_l_p8v8i32(<8 x i32>* %p) #2 { 246; CHECK-LABEL: test_l_p8v8i32: 247; CHECK: # %bb.0: # %entry 248; CHECK-NEXT: li 4, 16 249; CHECK-NEXT: lxvw4x 34, 0, 3 250; CHECK-NEXT: lxvw4x 35, 3, 4 251; CHECK-NEXT: blr 252entry: 253 %r = load <8 x i32>, <8 x i32>* %p, align 4 254 ret <8 x i32> %r 255 256} 257 258define <2 x i64> @test_l_p8v2i64(<2 x i64>* %p) #2 { 259; CHECK-LABEL: test_l_p8v2i64: 260; CHECK: # %bb.0: # %entry 261; CHECK-NEXT: lxvd2x 34, 0, 3 262; CHECK-NEXT: blr 263entry: 264 %r = load <2 x i64>, <2 x i64>* %p, align 8 265 ret <2 x i64> %r 266 267} 268 269define <4 x i64> @test_l_p8v4i64(<4 x i64>* %p) #2 { 270; CHECK-LABEL: test_l_p8v4i64: 271; CHECK: # %bb.0: # %entry 272; CHECK-NEXT: li 4, 16 273; CHECK-NEXT: lxvd2x 34, 0, 3 274; CHECK-NEXT: lxvd2x 35, 3, 4 275; CHECK-NEXT: blr 276entry: 277 %r = load <4 x i64>, <4 x i64>* %p, align 8 278 ret <4 x i64> %r 279 280} 281 282define <4 x float> @test_l_p8v4float(<4 x float>* %p) #2 { 283; CHECK-LABEL: test_l_p8v4float: 284; CHECK: # %bb.0: # %entry 285; CHECK-NEXT: lxvw4x 34, 0, 3 286; CHECK-NEXT: blr 287entry: 288 %r = load <4 x float>, <4 x float>* %p, align 4 289 ret <4 x float> %r 290 291} 292 293define <8 x float> @test_l_p8v8float(<8 x float>* %p) #2 { 294; CHECK-LABEL: test_l_p8v8float: 295; CHECK: # %bb.0: # %entry 296; CHECK-NEXT: li 4, 16 297; CHECK-NEXT: lxvw4x 34, 0, 3 298; CHECK-NEXT: lxvw4x 35, 3, 4 299; CHECK-NEXT: blr 300entry: 301 %r = load <8 x float>, <8 x float>* %p, align 4 302 ret <8 x float> %r 303 304} 305 306define <2 x double> @test_l_p8v2double(<2 x double>* %p) #2 { 307; CHECK-LABEL: test_l_p8v2double: 308; CHECK: # %bb.0: # %entry 309; CHECK-NEXT: lxvd2x 34, 0, 3 310; CHECK-NEXT: blr 311entry: 312 %r = load <2 x double>, <2 x double>* %p, align 8 313 ret <2 x double> %r 314 315} 316 317define <4 x double> @test_l_p8v4double(<4 x double>* %p) #2 { 318; CHECK-LABEL: test_l_p8v4double: 319; CHECK: # %bb.0: # %entry 320; CHECK-NEXT: li 4, 16 321; CHECK-NEXT: lxvd2x 34, 0, 3 322; CHECK-NEXT: lxvd2x 35, 3, 4 323; CHECK-NEXT: blr 324entry: 325 %r = load <4 x double>, <4 x double>* %p, align 8 326 ret <4 x double> %r 327 328} 329 330define void @test_s_v16i8(<16 x i8>* %p, <16 x i8> %v) #0 { 331; CHECK-LABEL: test_s_v16i8: 332; CHECK: # %bb.0: # %entry 333; CHECK-NEXT: stxvw4x 34, 0, 3 334; CHECK-NEXT: blr 335entry: 336 store <16 x i8> %v, <16 x i8>* %p, align 1 337 ret void 338 339} 340 341define void @test_s_v32i8(<32 x i8>* %p, <32 x i8> %v) #0 { 342; CHECK-LABEL: test_s_v32i8: 343; CHECK: # %bb.0: # %entry 344; CHECK-NEXT: li 4, 16 345; CHECK-NEXT: stxvw4x 34, 0, 3 346; CHECK-NEXT: stxvw4x 35, 3, 4 347; CHECK-NEXT: blr 348entry: 349 store <32 x i8> %v, <32 x i8>* %p, align 1 350 ret void 351 352} 353 354define void @test_s_v8i16(<8 x i16>* %p, <8 x i16> %v) #0 { 355; CHECK-LABEL: test_s_v8i16: 356; CHECK: # %bb.0: # %entry 357; CHECK-NEXT: stxvw4x 34, 0, 3 358; CHECK-NEXT: blr 359entry: 360 store <8 x i16> %v, <8 x i16>* %p, align 2 361 ret void 362 363} 364 365define void @test_s_v16i16(<16 x i16>* %p, <16 x i16> %v) #0 { 366; CHECK-LABEL: test_s_v16i16: 367; CHECK: # %bb.0: # %entry 368; CHECK-NEXT: li 4, 16 369; CHECK-NEXT: stxvw4x 34, 0, 3 370; CHECK-NEXT: stxvw4x 35, 3, 4 371; CHECK-NEXT: blr 372entry: 373 store <16 x i16> %v, <16 x i16>* %p, align 2 374 ret void 375 376} 377 378define void @test_s_v4i32(<4 x i32>* %p, <4 x i32> %v) #0 { 379; CHECK-LABEL: test_s_v4i32: 380; CHECK: # %bb.0: # %entry 381; CHECK-NEXT: stxvw4x 34, 0, 3 382; CHECK-NEXT: blr 383entry: 384 store <4 x i32> %v, <4 x i32>* %p, align 4 385 ret void 386 387} 388 389define void @test_s_v8i32(<8 x i32>* %p, <8 x i32> %v) #0 { 390; CHECK-LABEL: test_s_v8i32: 391; CHECK: # %bb.0: # %entry 392; CHECK-NEXT: li 4, 16 393; CHECK-NEXT: stxvw4x 34, 0, 3 394; CHECK-NEXT: stxvw4x 35, 3, 4 395; CHECK-NEXT: blr 396entry: 397 store <8 x i32> %v, <8 x i32>* %p, align 4 398 ret void 399 400} 401 402define void @test_s_v2i64(<2 x i64>* %p, <2 x i64> %v) #0 { 403; CHECK-LABEL: test_s_v2i64: 404; CHECK: # %bb.0: # %entry 405; CHECK-NEXT: stxvd2x 34, 0, 3 406; CHECK-NEXT: blr 407entry: 408 store <2 x i64> %v, <2 x i64>* %p, align 8 409 ret void 410 411} 412 413define void @test_s_v4i64(<4 x i64>* %p, <4 x i64> %v) #0 { 414; CHECK-LABEL: test_s_v4i64: 415; CHECK: # %bb.0: # %entry 416; CHECK-NEXT: li 4, 16 417; CHECK-NEXT: stxvd2x 34, 0, 3 418; CHECK-NEXT: stxvd2x 35, 3, 4 419; CHECK-NEXT: blr 420entry: 421 store <4 x i64> %v, <4 x i64>* %p, align 8 422 ret void 423 424} 425 426define void @test_s_v4float(<4 x float>* %p, <4 x float> %v) #0 { 427; CHECK-LABEL: test_s_v4float: 428; CHECK: # %bb.0: # %entry 429; CHECK-NEXT: stxvw4x 34, 0, 3 430; CHECK-NEXT: blr 431entry: 432 store <4 x float> %v, <4 x float>* %p, align 4 433 ret void 434 435} 436 437define void @test_s_v8float(<8 x float>* %p, <8 x float> %v) #0 { 438; CHECK-LABEL: test_s_v8float: 439; CHECK: # %bb.0: # %entry 440; CHECK-NEXT: li 4, 16 441; CHECK-NEXT: stxvw4x 34, 0, 3 442; CHECK-NEXT: stxvw4x 35, 3, 4 443; CHECK-NEXT: blr 444entry: 445 store <8 x float> %v, <8 x float>* %p, align 4 446 ret void 447 448} 449 450define void @test_s_v2double(<2 x double>* %p, <2 x double> %v) #0 { 451; CHECK-LABEL: test_s_v2double: 452; CHECK: # %bb.0: # %entry 453; CHECK-NEXT: stxvd2x 34, 0, 3 454; CHECK-NEXT: blr 455entry: 456 store <2 x double> %v, <2 x double>* %p, align 8 457 ret void 458 459} 460 461define void @test_s_v4double(<4 x double>* %p, <4 x double> %v) #0 { 462; CHECK-LABEL: test_s_v4double: 463; CHECK: # %bb.0: # %entry 464; CHECK-NEXT: li 4, 16 465; CHECK-NEXT: stxvd2x 34, 0, 3 466; CHECK-NEXT: stxvd2x 35, 3, 4 467; CHECK-NEXT: blr 468entry: 469 store <4 x double> %v, <4 x double>* %p, align 8 470 ret void 471 472} 473 474attributes #0 = { nounwind "target-cpu"="pwr7" } 475attributes #2 = { nounwind "target-cpu"="pwr8" } 476 477