1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE 4 5define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) { 6; CHECK-LE-LABEL: test1: 7; CHECK-LE: # %bb.0: # %entry 8; CHECK-LE-NEXT: vextubrx 3, 5, 2 9; CHECK-LE-NEXT: clrldi 3, 3, 56 10; CHECK-LE-NEXT: blr 11; CHECK-BE-LABEL: test1: 12; CHECK-BE: # %bb.0: # %entry 13; CHECK-BE-NEXT: vextublx 3, 5, 2 14; CHECK-BE-NEXT: clrldi 3, 3, 56 15; CHECK-BE-NEXT: blr 16 17entry: 18 %vecext = extractelement <16 x i8> %a, i32 %index 19 ret i8 %vecext 20} 21 22define signext i8 @test2(<16 x i8> %a, i32 signext %index) { 23; CHECK-LE-LABEL: test2: 24; CHECK-LE: # %bb.0: # %entry 25; CHECK-LE-NEXT: vextubrx 3, 5, 2 26; CHECK-LE-NEXT: extsb 3, 3 27; CHECK-LE-NEXT: blr 28; CHECK-BE-LABEL: test2: 29; CHECK-BE: # %bb.0: # %entry 30; CHECK-BE-NEXT: vextublx 3, 5, 2 31; CHECK-BE-NEXT: extsb 3, 3 32; CHECK-BE-NEXT: blr 33 34entry: 35 %vecext = extractelement <16 x i8> %a, i32 %index 36 ret i8 %vecext 37} 38 39define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) { 40; CHECK-LE-LABEL: test3: 41; CHECK-LE: # %bb.0: # %entry 42; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 43; CHECK-LE-NEXT: vextuhrx 3, 3, 2 44; CHECK-LE-NEXT: clrldi 3, 3, 48 45; CHECK-LE-NEXT: blr 46; CHECK-BE-LABEL: test3: 47; CHECK-BE: # %bb.0: # %entry 48; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 49; CHECK-BE-NEXT: vextuhlx 3, 3, 2 50; CHECK-BE-NEXT: clrldi 3, 3, 48 51; CHECK-BE-NEXT: blr 52 53entry: 54 %vecext = extractelement <8 x i16> %a, i32 %index 55 ret i16 %vecext 56} 57 58define signext i16 @test4(<8 x i16> %a, i32 signext %index) { 59; CHECK-LE-LABEL: test4: 60; CHECK-LE: # %bb.0: # %entry 61; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 62; CHECK-LE-NEXT: vextuhrx 3, 3, 2 63; CHECK-LE-NEXT: extsh 3, 3 64; CHECK-LE-NEXT: blr 65; CHECK-BE-LABEL: test4: 66; CHECK-BE: # %bb.0: # %entry 67; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 68; CHECK-BE-NEXT: vextuhlx 3, 3, 2 69; CHECK-BE-NEXT: extsh 3, 3 70; CHECK-BE-NEXT: blr 71 72entry: 73 %vecext = extractelement <8 x i16> %a, i32 %index 74 ret i16 %vecext 75} 76 77define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) { 78; CHECK-LE-LABEL: test5: 79; CHECK-LE: # %bb.0: # %entry 80; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 81; CHECK-LE-NEXT: vextuwrx 3, 3, 2 82; CHECK-LE-NEXT: blr 83; CHECK-BE-LABEL: test5: 84; CHECK-BE: # %bb.0: # %entry 85; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 86; CHECK-BE-NEXT: vextuwlx 3, 3, 2 87; CHECK-BE-NEXT: blr 88 89entry: 90 %vecext = extractelement <4 x i32> %a, i32 %index 91 ret i32 %vecext 92} 93 94define signext i32 @test6(<4 x i32> %a, i32 signext %index) { 95; CHECK-LE-LABEL: test6: 96; CHECK-LE: # %bb.0: # %entry 97; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 98; CHECK-LE-NEXT: vextuwrx 3, 3, 2 99; CHECK-LE-NEXT: extsw 3, 3 100; CHECK-LE-NEXT: blr 101; CHECK-BE-LABEL: test6: 102; CHECK-BE: # %bb.0: # %entry 103; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 104; CHECK-BE-NEXT: vextuwlx 3, 3, 2 105; CHECK-BE-NEXT: extsw 3, 3 106; CHECK-BE-NEXT: blr 107 108entry: 109 %vecext = extractelement <4 x i32> %a, i32 %index 110 ret i32 %vecext 111} 112 113; Test with immediate index 114define zeroext i8 @test7(<16 x i8> %a) { 115; CHECK-LE-LABEL: test7: 116; CHECK-LE: # %bb.0: # %entry 117; CHECK-LE-NEXT: li 3, 1 118; CHECK-LE-NEXT: vextubrx 3, 3, 2 119; CHECK-LE-NEXT: clrldi 3, 3, 56 120; CHECK-LE-NEXT: blr 121; CHECK-BE-LABEL: test7: 122; CHECK-BE: # %bb.0: # %entry 123; CHECK-BE-NEXT: li 3, 1 124; CHECK-BE-NEXT: vextublx 3, 3, 2 125; CHECK-BE-NEXT: clrldi 3, 3, 56 126; CHECK-BE-NEXT: blr 127 128entry: 129 %vecext = extractelement <16 x i8> %a, i32 1 130 ret i8 %vecext 131} 132 133define zeroext i16 @test8(<8 x i16> %a) { 134; CHECK-LE-LABEL: test8: 135; CHECK-LE: # %bb.0: # %entry 136; CHECK-LE-NEXT: li 3, 2 137; CHECK-LE-NEXT: vextuhrx 3, 3, 2 138; CHECK-LE-NEXT: clrldi 3, 3, 48 139; CHECK-LE-NEXT: blr 140; CHECK-BE-LABEL: test8: 141; CHECK-BE: # %bb.0: # %entry 142; CHECK-BE-NEXT: li 3, 2 143; CHECK-BE-NEXT: vextuhlx 3, 3, 2 144; CHECK-BE-NEXT: clrldi 3, 3, 48 145; CHECK-BE-NEXT: blr 146 147entry: 148 %vecext = extractelement <8 x i16> %a, i32 1 149 ret i16 %vecext 150} 151 152define zeroext i32 @test9(<4 x i32> %a) { 153; CHECK-LE-LABEL: test9: 154; CHECK-LE: # %bb.0: # %entry 155; CHECK-LE-NEXT: li 3, 12 156; CHECK-LE-NEXT: vextuwrx 3, 3, 2 157; CHECK-LE-NEXT: blr 158; CHECK-BE-LABEL: test9: 159; CHECK-BE: # %bb.0: # %entry 160; CHECK-BE-NEXT: li 3, 12 161; CHECK-BE-NEXT: vextuwlx 3, 3, 2 162; CHECK-BE-NEXT: blr 163 164entry: 165 %vecext = extractelement <4 x i32> %a, i32 3 166 ret i32 %vecext 167} 168