1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr9 \ 3; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ 4; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s 5 6; Function Attrs: nounwind readnone 7define <4 x i32> @test1(i8* %a) { 8; CHECK-LABEL: test1: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: lxvw4x v2, 0, r3 11; CHECK-NEXT: blr 12 entry: 13 %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a) 14 ret <4 x i32> %0 15} 16; Function Attrs: nounwind readnone 17declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*) 18 19; Function Attrs: nounwind readnone 20define <2 x double> @test2(i8* %a) { 21; CHECK-LABEL: test2: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: lxvd2x v2, 0, r3 24; CHECK-NEXT: blr 25 entry: 26 %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a) 27 ret <2 x double> %0 28} 29; Function Attrs: nounwind readnone 30declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*) 31 32; Function Attrs: nounwind readnone 33define void @test3(<4 x i32> %a, i8* %b) { 34; CHECK-LABEL: test3: 35; CHECK: # %bb.0: # %entry 36; CHECK-NEXT: stxvw4x v2, 0, r5 37; CHECK-NEXT: blr 38 entry: 39 tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b) 40 ret void 41} 42; Function Attrs: nounwind readnone 43declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*) 44 45; Function Attrs: nounwind readnone 46define void @test4(<2 x double> %a, i8* %b) { 47; CHECK-LABEL: test4: 48; CHECK: # %bb.0: # %entry 49; CHECK-NEXT: stxvd2x v2, 0, r5 50; CHECK-NEXT: blr 51 entry: 52 tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b) 53 ret void 54} 55; Function Attrs: nounwind readnone 56declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*) 57 58define i32 @test_vec_test_swdiv(<2 x double> %a, <2 x double> %b) { 59; CHECK-LABEL: test_vec_test_swdiv: 60; CHECK: # %bb.0: # %entry 61; CHECK-NEXT: xvtdivdp cr0, v2, v3 62; CHECK-NEXT: mfocrf r3, 128 63; CHECK-NEXT: srwi r3, r3, 28 64; CHECK-NEXT: blr 65 entry: 66 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b) 67 ret i32 %0 68} 69declare i32 @llvm.ppc.vsx.xvtdivdp(<2 x double>, <2 x double>) 70 71define i32 @test_vec_test_swdivs(<4 x float> %a, <4 x float> %b) { 72; CHECK-LABEL: test_vec_test_swdivs: 73; CHECK: # %bb.0: # %entry 74; CHECK-NEXT: xvtdivsp cr0, v2, v3 75; CHECK-NEXT: mfocrf r3, 128 76; CHECK-NEXT: srwi r3, r3, 28 77; CHECK-NEXT: blr 78 entry: 79 %0 = tail call i32 @llvm.ppc.vsx.xvtdivsp(<4 x float> %a, <4 x float> %b) 80 ret i32 %0 81} 82declare i32 @llvm.ppc.vsx.xvtdivsp(<4 x float>, <4 x float>) 83 84define i32 @test_vec_test_swsqrt(<2 x double> %a) { 85; CHECK-LABEL: test_vec_test_swsqrt: 86; CHECK: # %bb.0: # %entry 87; CHECK-NEXT: xvtsqrtdp cr0, v2 88; CHECK-NEXT: mfocrf r3, 128 89; CHECK-NEXT: srwi r3, r3, 28 90; CHECK-NEXT: blr 91 entry: 92 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %a) 93 ret i32 %0 94} 95declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>) 96 97define i32 @test_vec_test_swsqrts(<4 x float> %a) { 98; CHECK-LABEL: test_vec_test_swsqrts: 99; CHECK: # %bb.0: # %entry 100; CHECK-NEXT: xvtsqrtsp cr0, v2 101; CHECK-NEXT: mfocrf r3, 128 102; CHECK-NEXT: srwi r3, r3, 28 103; CHECK-NEXT: blr 104 entry: 105 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float> %a) 106 ret i32 %0 107} 108declare i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float>) 109 110define i32 @xvtdivdp_andi(<2 x double> %a, <2 x double> %b) { 111; CHECK-LABEL: xvtdivdp_andi: 112; CHECK: # %bb.0: # %entry 113; CHECK-NEXT: xvtdivdp cr0, v2, v3 114; CHECK-NEXT: li r4, 222 115; CHECK-NEXT: mfocrf r3, 128 116; CHECK-NEXT: srwi r3, r3, 28 117; CHECK-NEXT: andi. r3, r3, 2 118; CHECK-NEXT: li r3, 22 119; CHECK-NEXT: iseleq r3, r4, r3 120; CHECK-NEXT: blr 121 entry: 122 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b) 123 %1 = and i32 %0, 2 124 %cmp.not = icmp eq i32 %1, 0 125 %retval.0 = select i1 %cmp.not, i32 222, i32 22 126 ret i32 %retval.0 127} 128 129define i32 @xvtdivdp_shift(<2 x double> %a, <2 x double> %b) { 130; CHECK-LABEL: xvtdivdp_shift: 131; CHECK: # %bb.0: # %entry 132; CHECK-NEXT: xvtdivdp cr0, v2, v3 133; CHECK-NEXT: mfocrf r3, 128 134; CHECK-NEXT: li r3, 0 135; CHECK-NEXT: blr 136entry: 137 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b) 138 %1 = lshr i32 %0, 4 139 %.lobit = and i32 %1, 1 140 ret i32 %.lobit 141} 142