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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4
5declare i16 @llvm.bswap.i16(i16)
6declare i32 @llvm.bswap.i32(i32)
7declare i64 @llvm.bswap.i64(i64)
8declare i8 @llvm.cttz.i8(i8, i1)
9declare i16 @llvm.cttz.i16(i16, i1)
10declare i32 @llvm.cttz.i32(i32, i1)
11declare i64 @llvm.cttz.i64(i64, i1)
12declare i32 @llvm.ctlz.i32(i32, i1)
13declare i32 @llvm.ctpop.i32(i32)
14
15define i16 @test_bswap_i16(i16 %a) nounwind {
16; RV32I-LABEL: test_bswap_i16:
17; RV32I:       # %bb.0:
18; RV32I-NEXT:    slli a1, a0, 8
19; RV32I-NEXT:    lui a2, 4080
20; RV32I-NEXT:    and a1, a1, a2
21; RV32I-NEXT:    slli a0, a0, 24
22; RV32I-NEXT:    or a0, a0, a1
23; RV32I-NEXT:    srli a0, a0, 16
24; RV32I-NEXT:    ret
25  %tmp = call i16 @llvm.bswap.i16(i16 %a)
26  ret i16 %tmp
27}
28
29define i32 @test_bswap_i32(i32 %a) nounwind {
30; RV32I-LABEL: test_bswap_i32:
31; RV32I:       # %bb.0:
32; RV32I-NEXT:    srli a1, a0, 8
33; RV32I-NEXT:    lui a2, 16
34; RV32I-NEXT:    addi a2, a2, -256
35; RV32I-NEXT:    and a1, a1, a2
36; RV32I-NEXT:    srli a2, a0, 24
37; RV32I-NEXT:    or a1, a1, a2
38; RV32I-NEXT:    slli a2, a0, 8
39; RV32I-NEXT:    lui a3, 4080
40; RV32I-NEXT:    and a2, a2, a3
41; RV32I-NEXT:    slli a0, a0, 24
42; RV32I-NEXT:    or a0, a0, a2
43; RV32I-NEXT:    or a0, a0, a1
44; RV32I-NEXT:    ret
45  %tmp = call i32 @llvm.bswap.i32(i32 %a)
46  ret i32 %tmp
47}
48
49define i64 @test_bswap_i64(i64 %a) nounwind {
50; RV32I-LABEL: test_bswap_i64:
51; RV32I:       # %bb.0:
52; RV32I-NEXT:    srli a2, a1, 8
53; RV32I-NEXT:    lui a3, 16
54; RV32I-NEXT:    addi a3, a3, -256
55; RV32I-NEXT:    and a2, a2, a3
56; RV32I-NEXT:    srli a4, a1, 24
57; RV32I-NEXT:    or a2, a2, a4
58; RV32I-NEXT:    slli a4, a1, 8
59; RV32I-NEXT:    lui a5, 4080
60; RV32I-NEXT:    and a4, a4, a5
61; RV32I-NEXT:    slli a1, a1, 24
62; RV32I-NEXT:    or a1, a1, a4
63; RV32I-NEXT:    or a2, a1, a2
64; RV32I-NEXT:    srli a1, a0, 8
65; RV32I-NEXT:    and a1, a1, a3
66; RV32I-NEXT:    srli a3, a0, 24
67; RV32I-NEXT:    or a1, a1, a3
68; RV32I-NEXT:    slli a3, a0, 8
69; RV32I-NEXT:    and a3, a3, a5
70; RV32I-NEXT:    slli a0, a0, 24
71; RV32I-NEXT:    or a0, a0, a3
72; RV32I-NEXT:    or a1, a0, a1
73; RV32I-NEXT:    mv a0, a2
74; RV32I-NEXT:    ret
75  %tmp = call i64 @llvm.bswap.i64(i64 %a)
76  ret i64 %tmp
77}
78
79define i8 @test_cttz_i8(i8 %a) nounwind {
80; RV32I-LABEL: test_cttz_i8:
81; RV32I:       # %bb.0:
82; RV32I-NEXT:    addi sp, sp, -16
83; RV32I-NEXT:    sw ra, 12(sp)
84; RV32I-NEXT:    andi a1, a0, 255
85; RV32I-NEXT:    beqz a1, .LBB3_2
86; RV32I-NEXT:  # %bb.1: # %cond.false
87; RV32I-NEXT:    addi a1, a0, -1
88; RV32I-NEXT:    not a0, a0
89; RV32I-NEXT:    and a0, a0, a1
90; RV32I-NEXT:    srli a1, a0, 1
91; RV32I-NEXT:    lui a2, 349525
92; RV32I-NEXT:    addi a2, a2, 1365
93; RV32I-NEXT:    and a1, a1, a2
94; RV32I-NEXT:    sub a0, a0, a1
95; RV32I-NEXT:    lui a1, 209715
96; RV32I-NEXT:    addi a1, a1, 819
97; RV32I-NEXT:    and a2, a0, a1
98; RV32I-NEXT:    srli a0, a0, 2
99; RV32I-NEXT:    and a0, a0, a1
100; RV32I-NEXT:    add a0, a2, a0
101; RV32I-NEXT:    srli a1, a0, 4
102; RV32I-NEXT:    add a0, a0, a1
103; RV32I-NEXT:    lui a1, 61681
104; RV32I-NEXT:    addi a1, a1, -241
105; RV32I-NEXT:    and a0, a0, a1
106; RV32I-NEXT:    lui a1, 4112
107; RV32I-NEXT:    addi a1, a1, 257
108; RV32I-NEXT:    call __mulsi3
109; RV32I-NEXT:    srli a0, a0, 24
110; RV32I-NEXT:    j .LBB3_3
111; RV32I-NEXT:  .LBB3_2:
112; RV32I-NEXT:    addi a0, zero, 8
113; RV32I-NEXT:  .LBB3_3: # %cond.end
114; RV32I-NEXT:    lw ra, 12(sp)
115; RV32I-NEXT:    addi sp, sp, 16
116; RV32I-NEXT:    ret
117  %tmp = call i8 @llvm.cttz.i8(i8 %a, i1 false)
118  ret i8 %tmp
119}
120
121define i16 @test_cttz_i16(i16 %a) nounwind {
122; RV32I-LABEL: test_cttz_i16:
123; RV32I:       # %bb.0:
124; RV32I-NEXT:    addi sp, sp, -16
125; RV32I-NEXT:    sw ra, 12(sp)
126; RV32I-NEXT:    lui a1, 16
127; RV32I-NEXT:    addi a1, a1, -1
128; RV32I-NEXT:    and a1, a0, a1
129; RV32I-NEXT:    beqz a1, .LBB4_2
130; RV32I-NEXT:  # %bb.1: # %cond.false
131; RV32I-NEXT:    addi a1, a0, -1
132; RV32I-NEXT:    not a0, a0
133; RV32I-NEXT:    and a0, a0, a1
134; RV32I-NEXT:    srli a1, a0, 1
135; RV32I-NEXT:    lui a2, 349525
136; RV32I-NEXT:    addi a2, a2, 1365
137; RV32I-NEXT:    and a1, a1, a2
138; RV32I-NEXT:    sub a0, a0, a1
139; RV32I-NEXT:    lui a1, 209715
140; RV32I-NEXT:    addi a1, a1, 819
141; RV32I-NEXT:    and a2, a0, a1
142; RV32I-NEXT:    srli a0, a0, 2
143; RV32I-NEXT:    and a0, a0, a1
144; RV32I-NEXT:    add a0, a2, a0
145; RV32I-NEXT:    srli a1, a0, 4
146; RV32I-NEXT:    add a0, a0, a1
147; RV32I-NEXT:    lui a1, 61681
148; RV32I-NEXT:    addi a1, a1, -241
149; RV32I-NEXT:    and a0, a0, a1
150; RV32I-NEXT:    lui a1, 4112
151; RV32I-NEXT:    addi a1, a1, 257
152; RV32I-NEXT:    call __mulsi3
153; RV32I-NEXT:    srli a0, a0, 24
154; RV32I-NEXT:    j .LBB4_3
155; RV32I-NEXT:  .LBB4_2:
156; RV32I-NEXT:    addi a0, zero, 16
157; RV32I-NEXT:  .LBB4_3: # %cond.end
158; RV32I-NEXT:    lw ra, 12(sp)
159; RV32I-NEXT:    addi sp, sp, 16
160; RV32I-NEXT:    ret
161  %tmp = call i16 @llvm.cttz.i16(i16 %a, i1 false)
162  ret i16 %tmp
163}
164
165define i32 @test_cttz_i32(i32 %a) nounwind {
166; RV32I-LABEL: test_cttz_i32:
167; RV32I:       # %bb.0:
168; RV32I-NEXT:    addi sp, sp, -16
169; RV32I-NEXT:    sw ra, 12(sp)
170; RV32I-NEXT:    beqz a0, .LBB5_2
171; RV32I-NEXT:  # %bb.1: # %cond.false
172; RV32I-NEXT:    addi a1, a0, -1
173; RV32I-NEXT:    not a0, a0
174; RV32I-NEXT:    and a0, a0, a1
175; RV32I-NEXT:    srli a1, a0, 1
176; RV32I-NEXT:    lui a2, 349525
177; RV32I-NEXT:    addi a2, a2, 1365
178; RV32I-NEXT:    and a1, a1, a2
179; RV32I-NEXT:    sub a0, a0, a1
180; RV32I-NEXT:    lui a1, 209715
181; RV32I-NEXT:    addi a1, a1, 819
182; RV32I-NEXT:    and a2, a0, a1
183; RV32I-NEXT:    srli a0, a0, 2
184; RV32I-NEXT:    and a0, a0, a1
185; RV32I-NEXT:    add a0, a2, a0
186; RV32I-NEXT:    srli a1, a0, 4
187; RV32I-NEXT:    add a0, a0, a1
188; RV32I-NEXT:    lui a1, 61681
189; RV32I-NEXT:    addi a1, a1, -241
190; RV32I-NEXT:    and a0, a0, a1
191; RV32I-NEXT:    lui a1, 4112
192; RV32I-NEXT:    addi a1, a1, 257
193; RV32I-NEXT:    call __mulsi3
194; RV32I-NEXT:    srli a0, a0, 24
195; RV32I-NEXT:    j .LBB5_3
196; RV32I-NEXT:  .LBB5_2:
197; RV32I-NEXT:    addi a0, zero, 32
198; RV32I-NEXT:  .LBB5_3: # %cond.end
199; RV32I-NEXT:    lw ra, 12(sp)
200; RV32I-NEXT:    addi sp, sp, 16
201; RV32I-NEXT:    ret
202  %tmp = call i32 @llvm.cttz.i32(i32 %a, i1 false)
203  ret i32 %tmp
204}
205
206define i32 @test_ctlz_i32(i32 %a) nounwind {
207; RV32I-LABEL: test_ctlz_i32:
208; RV32I:       # %bb.0:
209; RV32I-NEXT:    addi sp, sp, -16
210; RV32I-NEXT:    sw ra, 12(sp)
211; RV32I-NEXT:    beqz a0, .LBB6_2
212; RV32I-NEXT:  # %bb.1: # %cond.false
213; RV32I-NEXT:    srli a1, a0, 1
214; RV32I-NEXT:    or a0, a0, a1
215; RV32I-NEXT:    srli a1, a0, 2
216; RV32I-NEXT:    or a0, a0, a1
217; RV32I-NEXT:    srli a1, a0, 4
218; RV32I-NEXT:    or a0, a0, a1
219; RV32I-NEXT:    srli a1, a0, 8
220; RV32I-NEXT:    or a0, a0, a1
221; RV32I-NEXT:    srli a1, a0, 16
222; RV32I-NEXT:    or a0, a0, a1
223; RV32I-NEXT:    not a0, a0
224; RV32I-NEXT:    srli a1, a0, 1
225; RV32I-NEXT:    lui a2, 349525
226; RV32I-NEXT:    addi a2, a2, 1365
227; RV32I-NEXT:    and a1, a1, a2
228; RV32I-NEXT:    sub a0, a0, a1
229; RV32I-NEXT:    lui a1, 209715
230; RV32I-NEXT:    addi a1, a1, 819
231; RV32I-NEXT:    and a2, a0, a1
232; RV32I-NEXT:    srli a0, a0, 2
233; RV32I-NEXT:    and a0, a0, a1
234; RV32I-NEXT:    add a0, a2, a0
235; RV32I-NEXT:    srli a1, a0, 4
236; RV32I-NEXT:    add a0, a0, a1
237; RV32I-NEXT:    lui a1, 61681
238; RV32I-NEXT:    addi a1, a1, -241
239; RV32I-NEXT:    and a0, a0, a1
240; RV32I-NEXT:    lui a1, 4112
241; RV32I-NEXT:    addi a1, a1, 257
242; RV32I-NEXT:    call __mulsi3
243; RV32I-NEXT:    srli a0, a0, 24
244; RV32I-NEXT:    j .LBB6_3
245; RV32I-NEXT:  .LBB6_2:
246; RV32I-NEXT:    addi a0, zero, 32
247; RV32I-NEXT:  .LBB6_3: # %cond.end
248; RV32I-NEXT:    lw ra, 12(sp)
249; RV32I-NEXT:    addi sp, sp, 16
250; RV32I-NEXT:    ret
251  %tmp = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
252  ret i32 %tmp
253}
254
255define i64 @test_cttz_i64(i64 %a) nounwind {
256; RV32I-LABEL: test_cttz_i64:
257; RV32I:       # %bb.0:
258; RV32I-NEXT:    addi sp, sp, -32
259; RV32I-NEXT:    sw ra, 28(sp)
260; RV32I-NEXT:    sw s0, 24(sp)
261; RV32I-NEXT:    sw s1, 20(sp)
262; RV32I-NEXT:    sw s2, 16(sp)
263; RV32I-NEXT:    sw s3, 12(sp)
264; RV32I-NEXT:    sw s4, 8(sp)
265; RV32I-NEXT:    sw s5, 4(sp)
266; RV32I-NEXT:    sw s6, 0(sp)
267; RV32I-NEXT:    mv s3, a1
268; RV32I-NEXT:    mv s4, a0
269; RV32I-NEXT:    addi a0, a0, -1
270; RV32I-NEXT:    not a1, s4
271; RV32I-NEXT:    and a0, a1, a0
272; RV32I-NEXT:    srli a1, a0, 1
273; RV32I-NEXT:    lui a2, 349525
274; RV32I-NEXT:    addi s5, a2, 1365
275; RV32I-NEXT:    and a1, a1, s5
276; RV32I-NEXT:    sub a0, a0, a1
277; RV32I-NEXT:    lui a1, 209715
278; RV32I-NEXT:    addi s0, a1, 819
279; RV32I-NEXT:    and a1, a0, s0
280; RV32I-NEXT:    srli a0, a0, 2
281; RV32I-NEXT:    and a0, a0, s0
282; RV32I-NEXT:    add a0, a1, a0
283; RV32I-NEXT:    srli a1, a0, 4
284; RV32I-NEXT:    add a0, a0, a1
285; RV32I-NEXT:    lui a1, 61681
286; RV32I-NEXT:    addi s6, a1, -241
287; RV32I-NEXT:    and a0, a0, s6
288; RV32I-NEXT:    lui a1, 4112
289; RV32I-NEXT:    addi s1, a1, 257
290; RV32I-NEXT:    mv a1, s1
291; RV32I-NEXT:    call __mulsi3
292; RV32I-NEXT:    mv s2, a0
293; RV32I-NEXT:    addi a0, s3, -1
294; RV32I-NEXT:    not a1, s3
295; RV32I-NEXT:    and a0, a1, a0
296; RV32I-NEXT:    srli a1, a0, 1
297; RV32I-NEXT:    and a1, a1, s5
298; RV32I-NEXT:    sub a0, a0, a1
299; RV32I-NEXT:    and a1, a0, s0
300; RV32I-NEXT:    srli a0, a0, 2
301; RV32I-NEXT:    and a0, a0, s0
302; RV32I-NEXT:    add a0, a1, a0
303; RV32I-NEXT:    srli a1, a0, 4
304; RV32I-NEXT:    add a0, a0, a1
305; RV32I-NEXT:    and a0, a0, s6
306; RV32I-NEXT:    mv a1, s1
307; RV32I-NEXT:    call __mulsi3
308; RV32I-NEXT:    bnez s4, .LBB7_2
309; RV32I-NEXT:  # %bb.1:
310; RV32I-NEXT:    srli a0, a0, 24
311; RV32I-NEXT:    addi a0, a0, 32
312; RV32I-NEXT:    j .LBB7_3
313; RV32I-NEXT:  .LBB7_2:
314; RV32I-NEXT:    srli a0, s2, 24
315; RV32I-NEXT:  .LBB7_3:
316; RV32I-NEXT:    mv a1, zero
317; RV32I-NEXT:    lw s6, 0(sp)
318; RV32I-NEXT:    lw s5, 4(sp)
319; RV32I-NEXT:    lw s4, 8(sp)
320; RV32I-NEXT:    lw s3, 12(sp)
321; RV32I-NEXT:    lw s2, 16(sp)
322; RV32I-NEXT:    lw s1, 20(sp)
323; RV32I-NEXT:    lw s0, 24(sp)
324; RV32I-NEXT:    lw ra, 28(sp)
325; RV32I-NEXT:    addi sp, sp, 32
326; RV32I-NEXT:    ret
327  %tmp = call i64 @llvm.cttz.i64(i64 %a, i1 false)
328  ret i64 %tmp
329}
330
331define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
332; RV32I-LABEL: test_cttz_i8_zero_undef:
333; RV32I:       # %bb.0:
334; RV32I-NEXT:    addi sp, sp, -16
335; RV32I-NEXT:    sw ra, 12(sp)
336; RV32I-NEXT:    addi a1, a0, -1
337; RV32I-NEXT:    not a0, a0
338; RV32I-NEXT:    and a0, a0, a1
339; RV32I-NEXT:    srli a1, a0, 1
340; RV32I-NEXT:    lui a2, 349525
341; RV32I-NEXT:    addi a2, a2, 1365
342; RV32I-NEXT:    and a1, a1, a2
343; RV32I-NEXT:    sub a0, a0, a1
344; RV32I-NEXT:    lui a1, 209715
345; RV32I-NEXT:    addi a1, a1, 819
346; RV32I-NEXT:    and a2, a0, a1
347; RV32I-NEXT:    srli a0, a0, 2
348; RV32I-NEXT:    and a0, a0, a1
349; RV32I-NEXT:    add a0, a2, a0
350; RV32I-NEXT:    srli a1, a0, 4
351; RV32I-NEXT:    add a0, a0, a1
352; RV32I-NEXT:    lui a1, 61681
353; RV32I-NEXT:    addi a1, a1, -241
354; RV32I-NEXT:    and a0, a0, a1
355; RV32I-NEXT:    lui a1, 4112
356; RV32I-NEXT:    addi a1, a1, 257
357; RV32I-NEXT:    call __mulsi3
358; RV32I-NEXT:    srli a0, a0, 24
359; RV32I-NEXT:    lw ra, 12(sp)
360; RV32I-NEXT:    addi sp, sp, 16
361; RV32I-NEXT:    ret
362  %tmp = call i8 @llvm.cttz.i8(i8 %a, i1 true)
363  ret i8 %tmp
364}
365
366define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
367; RV32I-LABEL: test_cttz_i16_zero_undef:
368; RV32I:       # %bb.0:
369; RV32I-NEXT:    addi sp, sp, -16
370; RV32I-NEXT:    sw ra, 12(sp)
371; RV32I-NEXT:    addi a1, a0, -1
372; RV32I-NEXT:    not a0, a0
373; RV32I-NEXT:    and a0, a0, a1
374; RV32I-NEXT:    srli a1, a0, 1
375; RV32I-NEXT:    lui a2, 349525
376; RV32I-NEXT:    addi a2, a2, 1365
377; RV32I-NEXT:    and a1, a1, a2
378; RV32I-NEXT:    sub a0, a0, a1
379; RV32I-NEXT:    lui a1, 209715
380; RV32I-NEXT:    addi a1, a1, 819
381; RV32I-NEXT:    and a2, a0, a1
382; RV32I-NEXT:    srli a0, a0, 2
383; RV32I-NEXT:    and a0, a0, a1
384; RV32I-NEXT:    add a0, a2, a0
385; RV32I-NEXT:    srli a1, a0, 4
386; RV32I-NEXT:    add a0, a0, a1
387; RV32I-NEXT:    lui a1, 61681
388; RV32I-NEXT:    addi a1, a1, -241
389; RV32I-NEXT:    and a0, a0, a1
390; RV32I-NEXT:    lui a1, 4112
391; RV32I-NEXT:    addi a1, a1, 257
392; RV32I-NEXT:    call __mulsi3
393; RV32I-NEXT:    srli a0, a0, 24
394; RV32I-NEXT:    lw ra, 12(sp)
395; RV32I-NEXT:    addi sp, sp, 16
396; RV32I-NEXT:    ret
397  %tmp = call i16 @llvm.cttz.i16(i16 %a, i1 true)
398  ret i16 %tmp
399}
400
401define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
402; RV32I-LABEL: test_cttz_i32_zero_undef:
403; RV32I:       # %bb.0:
404; RV32I-NEXT:    addi sp, sp, -16
405; RV32I-NEXT:    sw ra, 12(sp)
406; RV32I-NEXT:    addi a1, a0, -1
407; RV32I-NEXT:    not a0, a0
408; RV32I-NEXT:    and a0, a0, a1
409; RV32I-NEXT:    srli a1, a0, 1
410; RV32I-NEXT:    lui a2, 349525
411; RV32I-NEXT:    addi a2, a2, 1365
412; RV32I-NEXT:    and a1, a1, a2
413; RV32I-NEXT:    sub a0, a0, a1
414; RV32I-NEXT:    lui a1, 209715
415; RV32I-NEXT:    addi a1, a1, 819
416; RV32I-NEXT:    and a2, a0, a1
417; RV32I-NEXT:    srli a0, a0, 2
418; RV32I-NEXT:    and a0, a0, a1
419; RV32I-NEXT:    add a0, a2, a0
420; RV32I-NEXT:    srli a1, a0, 4
421; RV32I-NEXT:    add a0, a0, a1
422; RV32I-NEXT:    lui a1, 61681
423; RV32I-NEXT:    addi a1, a1, -241
424; RV32I-NEXT:    and a0, a0, a1
425; RV32I-NEXT:    lui a1, 4112
426; RV32I-NEXT:    addi a1, a1, 257
427; RV32I-NEXT:    call __mulsi3
428; RV32I-NEXT:    srli a0, a0, 24
429; RV32I-NEXT:    lw ra, 12(sp)
430; RV32I-NEXT:    addi sp, sp, 16
431; RV32I-NEXT:    ret
432  %tmp = call i32 @llvm.cttz.i32(i32 %a, i1 true)
433  ret i32 %tmp
434}
435
436define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
437; RV32I-LABEL: test_cttz_i64_zero_undef:
438; RV32I:       # %bb.0:
439; RV32I-NEXT:    addi sp, sp, -32
440; RV32I-NEXT:    sw ra, 28(sp)
441; RV32I-NEXT:    sw s0, 24(sp)
442; RV32I-NEXT:    sw s1, 20(sp)
443; RV32I-NEXT:    sw s2, 16(sp)
444; RV32I-NEXT:    sw s3, 12(sp)
445; RV32I-NEXT:    sw s4, 8(sp)
446; RV32I-NEXT:    sw s5, 4(sp)
447; RV32I-NEXT:    sw s6, 0(sp)
448; RV32I-NEXT:    mv s3, a1
449; RV32I-NEXT:    mv s4, a0
450; RV32I-NEXT:    addi a0, a0, -1
451; RV32I-NEXT:    not a1, s4
452; RV32I-NEXT:    and a0, a1, a0
453; RV32I-NEXT:    srli a1, a0, 1
454; RV32I-NEXT:    lui a2, 349525
455; RV32I-NEXT:    addi s5, a2, 1365
456; RV32I-NEXT:    and a1, a1, s5
457; RV32I-NEXT:    sub a0, a0, a1
458; RV32I-NEXT:    lui a1, 209715
459; RV32I-NEXT:    addi s0, a1, 819
460; RV32I-NEXT:    and a1, a0, s0
461; RV32I-NEXT:    srli a0, a0, 2
462; RV32I-NEXT:    and a0, a0, s0
463; RV32I-NEXT:    add a0, a1, a0
464; RV32I-NEXT:    srli a1, a0, 4
465; RV32I-NEXT:    add a0, a0, a1
466; RV32I-NEXT:    lui a1, 61681
467; RV32I-NEXT:    addi s6, a1, -241
468; RV32I-NEXT:    and a0, a0, s6
469; RV32I-NEXT:    lui a1, 4112
470; RV32I-NEXT:    addi s1, a1, 257
471; RV32I-NEXT:    mv a1, s1
472; RV32I-NEXT:    call __mulsi3
473; RV32I-NEXT:    mv s2, a0
474; RV32I-NEXT:    addi a0, s3, -1
475; RV32I-NEXT:    not a1, s3
476; RV32I-NEXT:    and a0, a1, a0
477; RV32I-NEXT:    srli a1, a0, 1
478; RV32I-NEXT:    and a1, a1, s5
479; RV32I-NEXT:    sub a0, a0, a1
480; RV32I-NEXT:    and a1, a0, s0
481; RV32I-NEXT:    srli a0, a0, 2
482; RV32I-NEXT:    and a0, a0, s0
483; RV32I-NEXT:    add a0, a1, a0
484; RV32I-NEXT:    srli a1, a0, 4
485; RV32I-NEXT:    add a0, a0, a1
486; RV32I-NEXT:    and a0, a0, s6
487; RV32I-NEXT:    mv a1, s1
488; RV32I-NEXT:    call __mulsi3
489; RV32I-NEXT:    bnez s4, .LBB11_2
490; RV32I-NEXT:  # %bb.1:
491; RV32I-NEXT:    srli a0, a0, 24
492; RV32I-NEXT:    addi a0, a0, 32
493; RV32I-NEXT:    j .LBB11_3
494; RV32I-NEXT:  .LBB11_2:
495; RV32I-NEXT:    srli a0, s2, 24
496; RV32I-NEXT:  .LBB11_3:
497; RV32I-NEXT:    mv a1, zero
498; RV32I-NEXT:    lw s6, 0(sp)
499; RV32I-NEXT:    lw s5, 4(sp)
500; RV32I-NEXT:    lw s4, 8(sp)
501; RV32I-NEXT:    lw s3, 12(sp)
502; RV32I-NEXT:    lw s2, 16(sp)
503; RV32I-NEXT:    lw s1, 20(sp)
504; RV32I-NEXT:    lw s0, 24(sp)
505; RV32I-NEXT:    lw ra, 28(sp)
506; RV32I-NEXT:    addi sp, sp, 32
507; RV32I-NEXT:    ret
508  %tmp = call i64 @llvm.cttz.i64(i64 %a, i1 true)
509  ret i64 %tmp
510}
511
512define i32 @test_ctpop_i32(i32 %a) nounwind {
513; RV32I-LABEL: test_ctpop_i32:
514; RV32I:       # %bb.0:
515; RV32I-NEXT:    addi sp, sp, -16
516; RV32I-NEXT:    sw ra, 12(sp)
517; RV32I-NEXT:    srli a1, a0, 1
518; RV32I-NEXT:    lui a2, 349525
519; RV32I-NEXT:    addi a2, a2, 1365
520; RV32I-NEXT:    and a1, a1, a2
521; RV32I-NEXT:    sub a0, a0, a1
522; RV32I-NEXT:    lui a1, 209715
523; RV32I-NEXT:    addi a1, a1, 819
524; RV32I-NEXT:    and a2, a0, a1
525; RV32I-NEXT:    srli a0, a0, 2
526; RV32I-NEXT:    and a0, a0, a1
527; RV32I-NEXT:    add a0, a2, a0
528; RV32I-NEXT:    srli a1, a0, 4
529; RV32I-NEXT:    add a0, a0, a1
530; RV32I-NEXT:    lui a1, 61681
531; RV32I-NEXT:    addi a1, a1, -241
532; RV32I-NEXT:    and a0, a0, a1
533; RV32I-NEXT:    lui a1, 4112
534; RV32I-NEXT:    addi a1, a1, 257
535; RV32I-NEXT:    call __mulsi3
536; RV32I-NEXT:    srli a0, a0, 24
537; RV32I-NEXT:    lw ra, 12(sp)
538; RV32I-NEXT:    addi sp, sp, 16
539; RV32I-NEXT:    ret
540  %1 = call i32 @llvm.ctpop.i32(i32 %a)
541  ret i32 %1
542}
543