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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV64I %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \
5; RUN:    -verify-machineinstrs < %s \
6; RUN:   | FileCheck -check-prefix=RV64I %s
7
8; This file contains tests that should have identical output for the lp64 and
9; lp64f ABIs. It doesn't check codegen when frame pointer elimination is
10; disabled, as there is sufficient coverage for this case in other files.
11
12define i64 @callee_double_in_regs(i64 %a, double %b) nounwind {
13; RV64I-LABEL: callee_double_in_regs:
14; RV64I:       # %bb.0:
15; RV64I-NEXT:    addi sp, sp, -16
16; RV64I-NEXT:    sd ra, 8(sp)
17; RV64I-NEXT:    sd s0, 0(sp)
18; RV64I-NEXT:    mv s0, a0
19; RV64I-NEXT:    mv a0, a1
20; RV64I-NEXT:    call __fixdfdi
21; RV64I-NEXT:    add a0, s0, a0
22; RV64I-NEXT:    ld s0, 0(sp)
23; RV64I-NEXT:    ld ra, 8(sp)
24; RV64I-NEXT:    addi sp, sp, 16
25; RV64I-NEXT:    ret
26  %b_fptosi = fptosi double %b to i64
27  %1 = add i64 %a, %b_fptosi
28  ret i64 %1
29}
30
31define i64 @caller_double_in_regs() nounwind {
32; RV64I-LABEL: caller_double_in_regs:
33; RV64I:       # %bb.0:
34; RV64I-NEXT:    addi sp, sp, -16
35; RV64I-NEXT:    sd ra, 8(sp)
36; RV64I-NEXT:    addi a0, zero, 1
37; RV64I-NEXT:    slli a1, a0, 62
38; RV64I-NEXT:    addi a0, zero, 1
39; RV64I-NEXT:    call callee_double_in_regs
40; RV64I-NEXT:    ld ra, 8(sp)
41; RV64I-NEXT:    addi sp, sp, 16
42; RV64I-NEXT:    ret
43  %1 = call i64 @callee_double_in_regs(i64 1, double 2.0)
44  ret i64 %1
45}
46
47define double @callee_double_ret() nounwind {
48; RV64I-LABEL: callee_double_ret:
49; RV64I:       # %bb.0:
50; RV64I-NEXT:    addi a0, zero, 1023
51; RV64I-NEXT:    slli a0, a0, 52
52; RV64I-NEXT:    ret
53  ret double 1.0
54}
55
56define i64 @caller_double_ret() nounwind {
57; RV64I-LABEL: caller_double_ret:
58; RV64I:       # %bb.0:
59; RV64I-NEXT:    addi sp, sp, -16
60; RV64I-NEXT:    sd ra, 8(sp)
61; RV64I-NEXT:    call callee_double_ret
62; RV64I-NEXT:    ld ra, 8(sp)
63; RV64I-NEXT:    addi sp, sp, 16
64; RV64I-NEXT:    ret
65  %1 = call double @callee_double_ret()
66  %2 = bitcast double %1 to i64
67  ret i64 %2
68}
69