1; This test is designed to run twice, once with function attributes and once 2; with target attributes added on the command line. 3; 4; RUN: cat %s > %t.tgtattr 5; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr 6; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj \ 7; RUN: -disable-block-placement < %t.tgtattr \ 8; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \ 9; RUN: | FileCheck -check-prefix=RV32IC %s 10; 11; RUN: cat %s > %t.fnattr 12; RUN: echo 'attributes #0 = { nounwind "target-features"="+c" }' >> %t.fnattr 13; RUN: llc -mtriple=riscv32 -filetype=obj \ 14; RUN: -disable-block-placement < %t.fnattr \ 15; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \ 16; RUN: | FileCheck -check-prefix=RV32IC %s 17 18; This acts as a sanity check for the codegen instruction compression path, 19; verifying that the assembled file contains compressed instructions when 20; expected. Handling of the compressed ISA is implemented so the same 21; transformation patterns should be used whether compressing an input .s file or 22; compressing codegen output. This file contains sanity checks to ensure that is 23; working as expected. Particular care should be taken to test pseudo 24; instructions. 25 26; Note: TODOs in this file are only appropriate if they highlight a case where 27; a generated instruction that can be compressed by an existing pattern isn't. 28; It may be useful to have tests that indicate where better compression would be 29; possible if alternative codegen choices were made, but they belong in a 30; different test file. 31 32define i32 @simple_arith(i32 %a, i32 %b) #0 { 33; RV32IC-LABEL: <simple_arith>: 34; RV32IC: addi a2, a0, 1 35; RV32IC-NEXT: c.andi a2, 11 36; RV32IC-NEXT: c.slli a2, 7 37; RV32IC-NEXT: c.srai a1, 9 38; RV32IC-NEXT: c.add a1, a2 39; RV32IC-NEXT: sub a0, a1, a0 40; RV32IC-NEXT: c.jr ra 41 %1 = add i32 %a, 1 42 %2 = and i32 %1, 11 43 %3 = shl i32 %2, 7 44 %4 = ashr i32 %b, 9 45 %5 = add i32 %3, %4 46 %6 = sub i32 %5, %a 47 ret i32 %6 48} 49 50define i32 @select(i32 %a, i32 *%b) #0 { 51; RV32IC-LABEL: <select>: 52; RV32IC: c.lw a2, 0(a1) 53; RV32IC-NEXT: c.beqz a2, 0x18 54; RV32IC-NEXT: c.mv a0, a2 55; RV32IC-NEXT: c.lw a2, 0(a1) 56; RV32IC-NEXT: c.bnez a2, 0x1e 57; RV32IC-NEXT: c.mv a0, a2 58; RV32IC-NEXT: c.lw a2, 0(a1) 59; RV32IC-NEXT: bltu a2, a0, 0x26 60; RV32IC-NEXT: c.mv a0, a2 61; RV32IC-NEXT: c.lw a2, 0(a1) 62; RV32IC-NEXT: bgeu a0, a2, 0x2e 63; RV32IC-NEXT: c.mv a0, a2 64; RV32IC-NEXT: c.lw a2, 0(a1) 65; RV32IC-NEXT: bltu a0, a2, 0x36 66; RV32IC-NEXT: c.mv a0, a2 67; RV32IC-NEXT: c.lw a2, 0(a1) 68; RV32IC-NEXT: bgeu a2, a0, 0x3e 69; RV32IC-NEXT: c.mv a0, a2 70; RV32IC-NEXT: c.lw a2, 0(a1) 71; RV32IC-NEXT: blt a2, a0, 0x46 72; RV32IC-NEXT: c.mv a0, a2 73; RV32IC-NEXT: c.lw a2, 0(a1) 74; RV32IC-NEXT: bge a0, a2, 0x4e 75; RV32IC-NEXT: c.mv a0, a2 76; RV32IC-NEXT: c.lw a2, 0(a1) 77; RV32IC-NEXT: blt a0, a2, 0x56 78; RV32IC-NEXT: c.mv a0, a2 79; RV32IC-NEXT: c.lw a1, 0(a1) 80; RV32IC-NEXT: bge a1, a0, 0x5e 81; RV32IC-NEXT: c.mv a0, a1 82; RV32IC-NEXT: c.jr ra 83 %val1 = load volatile i32, i32* %b 84 %tst1 = icmp eq i32 0, %val1 85 %val2 = select i1 %tst1, i32 %a, i32 %val1 86 87 %val3 = load volatile i32, i32* %b 88 %tst2 = icmp ne i32 0, %val3 89 %val4 = select i1 %tst2, i32 %val2, i32 %val3 90 91 %val5 = load volatile i32, i32* %b 92 %tst3 = icmp ugt i32 %val4, %val5 93 %val6 = select i1 %tst3, i32 %val4, i32 %val5 94 95 %val7 = load volatile i32, i32* %b 96 %tst4 = icmp uge i32 %val6, %val7 97 %val8 = select i1 %tst4, i32 %val6, i32 %val7 98 99 %val9 = load volatile i32, i32* %b 100 %tst5 = icmp ult i32 %val8, %val9 101 %val10 = select i1 %tst5, i32 %val8, i32 %val9 102 103 %val11 = load volatile i32, i32* %b 104 %tst6 = icmp ule i32 %val10, %val11 105 %val12 = select i1 %tst6, i32 %val10, i32 %val11 106 107 %val13 = load volatile i32, i32* %b 108 %tst7 = icmp sgt i32 %val12, %val13 109 %val14 = select i1 %tst7, i32 %val12, i32 %val13 110 111 %val15 = load volatile i32, i32* %b 112 %tst8 = icmp sge i32 %val14, %val15 113 %val16 = select i1 %tst8, i32 %val14, i32 %val15 114 115 %val17 = load volatile i32, i32* %b 116 %tst9 = icmp slt i32 %val16, %val17 117 %val18 = select i1 %tst9, i32 %val16, i32 %val17 118 119 %val19 = load volatile i32, i32* %b 120 %tst10 = icmp sle i32 %val18, %val19 121 %val20 = select i1 %tst10, i32 %val18, i32 %val19 122 123 ret i32 %val20 124} 125 126define i32 @pos_tiny() #0 { 127; RV32IC-LABEL: <pos_tiny>: 128; RV32IC: c.li a0, 18 129; RV32IC-NEXT: c.jr ra 130 ret i32 18 131} 132 133define i32 @pos_i32() #0 { 134; RV32IC-LABEL: <pos_i32>: 135; RV32IC: lui a0, 423811 136; RV32IC-NEXT: addi a0, a0, -1297 137; RV32IC-NEXT: c.jr ra 138 ret i32 1735928559 139} 140 141define i32 @pos_i32_half_compressible() #0 { 142; RV32IC-LABEL: <pos_i32_half_compressible>: 143; RV32IC: lui a0, 423810 144; RV32IC-NEXT: c.addi a0, 28 145; RV32IC-NEXT: c.jr ra 146 ret i32 1735925788 147} 148 149define i32 @neg_tiny() #0 { 150; RV32IC-LABEL: <neg_tiny>: 151; RV32IC: c.li a0, -19 152; RV32IC-NEXT: c.jr ra 153 ret i32 -19 154} 155 156define i32 @neg_i32() #0 { 157; RV32IC-LABEL: <neg_i32>: 158; RV32IC: lui a0, 912092 159; RV32IC-NEXT: addi a0, a0, -273 160; RV32IC-NEXT: c.jr ra 161 ret i32 -559038737 162} 163 164define i32 @pos_i32_hi20_only() #0 { 165; RV32IC-LABEL: <pos_i32_hi20_only>: 166; RV32IC: c.lui a0, 16 167; RV32IC-NEXT: c.jr ra 168 ret i32 65536 169} 170 171define i32 @neg_i32_hi20_only() #0 { 172; RV32IC-LABEL: <neg_i32_hi20_only>: 173; RV32IC: c.lui a0, 1048560 174; RV32IC-NEXT: c.jr ra 175 ret i32 -65536 176} 177