1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ 3; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s 4; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh -verify-machineinstrs \ 5; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s 6; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ 7; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s 8; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh -verify-machineinstrs \ 9; RUN: -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s 10 11define i16 @fcvt_si_h(half %a) nounwind { 12; RV32IZFH-LABEL: fcvt_si_h: 13; RV32IZFH: # %bb.0: 14; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz 15; RV32IZFH-NEXT: ret 16; 17; RV32IDZFH-LABEL: fcvt_si_h: 18; RV32IDZFH: # %bb.0: 19; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz 20; RV32IDZFH-NEXT: ret 21; 22; RV64IZFH-LABEL: fcvt_si_h: 23; RV64IZFH: # %bb.0: 24; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz 25; RV64IZFH-NEXT: ret 26; 27; RV64IDZFH-LABEL: fcvt_si_h: 28; RV64IDZFH: # %bb.0: 29; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz 30; RV64IDZFH-NEXT: ret 31 %1 = fptosi half %a to i16 32 ret i16 %1 33} 34 35define i16 @fcvt_ui_h(half %a) nounwind { 36; RV32IZFH-LABEL: fcvt_ui_h: 37; RV32IZFH: # %bb.0: 38; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz 39; RV32IZFH-NEXT: ret 40; 41; RV32IDZFH-LABEL: fcvt_ui_h: 42; RV32IDZFH: # %bb.0: 43; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz 44; RV32IDZFH-NEXT: ret 45; 46; RV64IZFH-LABEL: fcvt_ui_h: 47; RV64IZFH: # %bb.0: 48; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz 49; RV64IZFH-NEXT: ret 50; 51; RV64IDZFH-LABEL: fcvt_ui_h: 52; RV64IDZFH: # %bb.0: 53; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz 54; RV64IDZFH-NEXT: ret 55 %1 = fptoui half %a to i16 56 ret i16 %1 57} 58 59define i32 @fcvt_w_h(half %a) nounwind { 60; RV32IZFH-LABEL: fcvt_w_h: 61; RV32IZFH: # %bb.0: 62; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz 63; RV32IZFH-NEXT: ret 64; 65; RV32IDZFH-LABEL: fcvt_w_h: 66; RV32IDZFH: # %bb.0: 67; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz 68; RV32IDZFH-NEXT: ret 69; 70; RV64IZFH-LABEL: fcvt_w_h: 71; RV64IZFH: # %bb.0: 72; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz 73; RV64IZFH-NEXT: ret 74; 75; RV64IDZFH-LABEL: fcvt_w_h: 76; RV64IDZFH: # %bb.0: 77; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz 78; RV64IDZFH-NEXT: ret 79 %1 = fptosi half %a to i32 80 ret i32 %1 81} 82 83define i32 @fcvt_wu_h(half %a) nounwind { 84; RV32IZFH-LABEL: fcvt_wu_h: 85; RV32IZFH: # %bb.0: 86; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz 87; RV32IZFH-NEXT: ret 88; 89; RV32IDZFH-LABEL: fcvt_wu_h: 90; RV32IDZFH: # %bb.0: 91; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz 92; RV32IDZFH-NEXT: ret 93; 94; RV64IZFH-LABEL: fcvt_wu_h: 95; RV64IZFH: # %bb.0: 96; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz 97; RV64IZFH-NEXT: ret 98; 99; RV64IDZFH-LABEL: fcvt_wu_h: 100; RV64IDZFH: # %bb.0: 101; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz 102; RV64IDZFH-NEXT: ret 103 %1 = fptoui half %a to i32 104 ret i32 %1 105} 106 107define i64 @fcvt_l_h(half %a) nounwind { 108; RV32IZFH-LABEL: fcvt_l_h: 109; RV32IZFH: # %bb.0: 110; RV32IZFH-NEXT: addi sp, sp, -16 111; RV32IZFH-NEXT: sw ra, 12(sp) 112; RV32IZFH-NEXT: call __fixhfdi 113; RV32IZFH-NEXT: lw ra, 12(sp) 114; RV32IZFH-NEXT: addi sp, sp, 16 115; RV32IZFH-NEXT: ret 116; 117; RV32IDZFH-LABEL: fcvt_l_h: 118; RV32IDZFH: # %bb.0: 119; RV32IDZFH-NEXT: addi sp, sp, -16 120; RV32IDZFH-NEXT: sw ra, 12(sp) 121; RV32IDZFH-NEXT: call __fixhfdi 122; RV32IDZFH-NEXT: lw ra, 12(sp) 123; RV32IDZFH-NEXT: addi sp, sp, 16 124; RV32IDZFH-NEXT: ret 125; 126; RV64IZFH-LABEL: fcvt_l_h: 127; RV64IZFH: # %bb.0: 128; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz 129; RV64IZFH-NEXT: ret 130; 131; RV64IDZFH-LABEL: fcvt_l_h: 132; RV64IDZFH: # %bb.0: 133; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz 134; RV64IDZFH-NEXT: ret 135 %1 = fptosi half %a to i64 136 ret i64 %1 137} 138 139define i64 @fcvt_lu_h(half %a) nounwind { 140; RV32IZFH-LABEL: fcvt_lu_h: 141; RV32IZFH: # %bb.0: 142; RV32IZFH-NEXT: addi sp, sp, -16 143; RV32IZFH-NEXT: sw ra, 12(sp) 144; RV32IZFH-NEXT: call __fixunshfdi 145; RV32IZFH-NEXT: lw ra, 12(sp) 146; RV32IZFH-NEXT: addi sp, sp, 16 147; RV32IZFH-NEXT: ret 148; 149; RV32IDZFH-LABEL: fcvt_lu_h: 150; RV32IDZFH: # %bb.0: 151; RV32IDZFH-NEXT: addi sp, sp, -16 152; RV32IDZFH-NEXT: sw ra, 12(sp) 153; RV32IDZFH-NEXT: call __fixunshfdi 154; RV32IDZFH-NEXT: lw ra, 12(sp) 155; RV32IDZFH-NEXT: addi sp, sp, 16 156; RV32IDZFH-NEXT: ret 157; 158; RV64IZFH-LABEL: fcvt_lu_h: 159; RV64IZFH: # %bb.0: 160; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz 161; RV64IZFH-NEXT: ret 162; 163; RV64IDZFH-LABEL: fcvt_lu_h: 164; RV64IDZFH: # %bb.0: 165; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz 166; RV64IDZFH-NEXT: ret 167 %1 = fptoui half %a to i64 168 ret i64 %1 169} 170 171define half @fcvt_h_si(i16 %a) nounwind { 172; RV32IZFH-LABEL: fcvt_h_si: 173; RV32IZFH: # %bb.0: 174; RV32IZFH-NEXT: slli a0, a0, 16 175; RV32IZFH-NEXT: srai a0, a0, 16 176; RV32IZFH-NEXT: fcvt.h.w fa0, a0 177; RV32IZFH-NEXT: ret 178; 179; RV32IDZFH-LABEL: fcvt_h_si: 180; RV32IDZFH: # %bb.0: 181; RV32IDZFH-NEXT: slli a0, a0, 16 182; RV32IDZFH-NEXT: srai a0, a0, 16 183; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 184; RV32IDZFH-NEXT: ret 185; 186; RV64IZFH-LABEL: fcvt_h_si: 187; RV64IZFH: # %bb.0: 188; RV64IZFH-NEXT: slli a0, a0, 48 189; RV64IZFH-NEXT: srai a0, a0, 48 190; RV64IZFH-NEXT: fcvt.h.l fa0, a0 191; RV64IZFH-NEXT: ret 192; 193; RV64IDZFH-LABEL: fcvt_h_si: 194; RV64IDZFH: # %bb.0: 195; RV64IDZFH-NEXT: slli a0, a0, 48 196; RV64IDZFH-NEXT: srai a0, a0, 48 197; RV64IDZFH-NEXT: fcvt.h.l fa0, a0 198; RV64IDZFH-NEXT: ret 199 %1 = sitofp i16 %a to half 200 ret half %1 201} 202 203define half @fcvt_h_ui(i16 %a) nounwind { 204; RV32IZFH-LABEL: fcvt_h_ui: 205; RV32IZFH: # %bb.0: 206; RV32IZFH-NEXT: lui a1, 16 207; RV32IZFH-NEXT: addi a1, a1, -1 208; RV32IZFH-NEXT: and a0, a0, a1 209; RV32IZFH-NEXT: fcvt.h.wu fa0, a0 210; RV32IZFH-NEXT: ret 211; 212; RV32IDZFH-LABEL: fcvt_h_ui: 213; RV32IDZFH: # %bb.0: 214; RV32IDZFH-NEXT: lui a1, 16 215; RV32IDZFH-NEXT: addi a1, a1, -1 216; RV32IDZFH-NEXT: and a0, a0, a1 217; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 218; RV32IDZFH-NEXT: ret 219; 220; RV64IZFH-LABEL: fcvt_h_ui: 221; RV64IZFH: # %bb.0: 222; RV64IZFH-NEXT: lui a1, 16 223; RV64IZFH-NEXT: addiw a1, a1, -1 224; RV64IZFH-NEXT: and a0, a0, a1 225; RV64IZFH-NEXT: fcvt.h.lu fa0, a0 226; RV64IZFH-NEXT: ret 227; 228; RV64IDZFH-LABEL: fcvt_h_ui: 229; RV64IDZFH: # %bb.0: 230; RV64IDZFH-NEXT: lui a1, 16 231; RV64IDZFH-NEXT: addiw a1, a1, -1 232; RV64IDZFH-NEXT: and a0, a0, a1 233; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0 234; RV64IDZFH-NEXT: ret 235 %1 = uitofp i16 %a to half 236 ret half %1 237} 238 239define half @fcvt_h_w(i32 %a) nounwind { 240; RV32IZFH-LABEL: fcvt_h_w: 241; RV32IZFH: # %bb.0: 242; RV32IZFH-NEXT: fcvt.h.w fa0, a0 243; RV32IZFH-NEXT: ret 244; 245; RV32IDZFH-LABEL: fcvt_h_w: 246; RV32IDZFH: # %bb.0: 247; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 248; RV32IDZFH-NEXT: ret 249; 250; RV64IZFH-LABEL: fcvt_h_w: 251; RV64IZFH: # %bb.0: 252; RV64IZFH-NEXT: fcvt.h.w fa0, a0 253; RV64IZFH-NEXT: ret 254; 255; RV64IDZFH-LABEL: fcvt_h_w: 256; RV64IDZFH: # %bb.0: 257; RV64IDZFH-NEXT: fcvt.h.w fa0, a0 258; RV64IDZFH-NEXT: ret 259 %1 = sitofp i32 %a to half 260 ret half %1 261} 262 263define half @fcvt_h_wu(i32 %a) nounwind { 264; RV32IZFH-LABEL: fcvt_h_wu: 265; RV32IZFH: # %bb.0: 266; RV32IZFH-NEXT: fcvt.h.wu fa0, a0 267; RV32IZFH-NEXT: ret 268; 269; RV32IDZFH-LABEL: fcvt_h_wu: 270; RV32IDZFH: # %bb.0: 271; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 272; RV32IDZFH-NEXT: ret 273; 274; RV64IZFH-LABEL: fcvt_h_wu: 275; RV64IZFH: # %bb.0: 276; RV64IZFH-NEXT: fcvt.h.wu fa0, a0 277; RV64IZFH-NEXT: ret 278; 279; RV64IDZFH-LABEL: fcvt_h_wu: 280; RV64IDZFH: # %bb.0: 281; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0 282; RV64IDZFH-NEXT: ret 283 %1 = uitofp i32 %a to half 284 ret half %1 285} 286 287define half @fcvt_h_l(i64 %a) nounwind { 288; RV32IZFH-LABEL: fcvt_h_l: 289; RV32IZFH: # %bb.0: 290; RV32IZFH-NEXT: addi sp, sp, -16 291; RV32IZFH-NEXT: sw ra, 12(sp) 292; RV32IZFH-NEXT: call __floatdihf 293; RV32IZFH-NEXT: lw ra, 12(sp) 294; RV32IZFH-NEXT: addi sp, sp, 16 295; RV32IZFH-NEXT: ret 296; 297; RV32IDZFH-LABEL: fcvt_h_l: 298; RV32IDZFH: # %bb.0: 299; RV32IDZFH-NEXT: addi sp, sp, -16 300; RV32IDZFH-NEXT: sw ra, 12(sp) 301; RV32IDZFH-NEXT: call __floatdihf 302; RV32IDZFH-NEXT: lw ra, 12(sp) 303; RV32IDZFH-NEXT: addi sp, sp, 16 304; RV32IDZFH-NEXT: ret 305; 306; RV64IZFH-LABEL: fcvt_h_l: 307; RV64IZFH: # %bb.0: 308; RV64IZFH-NEXT: fcvt.h.l fa0, a0 309; RV64IZFH-NEXT: ret 310; 311; RV64IDZFH-LABEL: fcvt_h_l: 312; RV64IDZFH: # %bb.0: 313; RV64IDZFH-NEXT: fcvt.h.l fa0, a0 314; RV64IDZFH-NEXT: ret 315 %1 = sitofp i64 %a to half 316 ret half %1 317} 318 319define half @fcvt_h_lu(i64 %a) nounwind { 320; RV32IZFH-LABEL: fcvt_h_lu: 321; RV32IZFH: # %bb.0: 322; RV32IZFH-NEXT: addi sp, sp, -16 323; RV32IZFH-NEXT: sw ra, 12(sp) 324; RV32IZFH-NEXT: call __floatundihf 325; RV32IZFH-NEXT: lw ra, 12(sp) 326; RV32IZFH-NEXT: addi sp, sp, 16 327; RV32IZFH-NEXT: ret 328; 329; RV32IDZFH-LABEL: fcvt_h_lu: 330; RV32IDZFH: # %bb.0: 331; RV32IDZFH-NEXT: addi sp, sp, -16 332; RV32IDZFH-NEXT: sw ra, 12(sp) 333; RV32IDZFH-NEXT: call __floatundihf 334; RV32IDZFH-NEXT: lw ra, 12(sp) 335; RV32IDZFH-NEXT: addi sp, sp, 16 336; RV32IDZFH-NEXT: ret 337; 338; RV64IZFH-LABEL: fcvt_h_lu: 339; RV64IZFH: # %bb.0: 340; RV64IZFH-NEXT: fcvt.h.lu fa0, a0 341; RV64IZFH-NEXT: ret 342; 343; RV64IDZFH-LABEL: fcvt_h_lu: 344; RV64IDZFH: # %bb.0: 345; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0 346; RV64IDZFH-NEXT: ret 347 %1 = uitofp i64 %a to half 348 ret half %1 349} 350 351define half @fcvt_h_s(float %a) nounwind { 352; RV32IZFH-LABEL: fcvt_h_s: 353; RV32IZFH: # %bb.0: 354; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 355; RV32IZFH-NEXT: ret 356; 357; RV32IDZFH-LABEL: fcvt_h_s: 358; RV32IDZFH: # %bb.0: 359; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0 360; RV32IDZFH-NEXT: ret 361; 362; RV64IZFH-LABEL: fcvt_h_s: 363; RV64IZFH: # %bb.0: 364; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 365; RV64IZFH-NEXT: ret 366; 367; RV64IDZFH-LABEL: fcvt_h_s: 368; RV64IDZFH: # %bb.0: 369; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0 370; RV64IDZFH-NEXT: ret 371 %1 = fptrunc float %a to half 372 ret half %1 373} 374 375define float @fcvt_s_h(half %a) nounwind { 376; RV32IZFH-LABEL: fcvt_s_h: 377; RV32IZFH: # %bb.0: 378; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 379; RV32IZFH-NEXT: ret 380; 381; RV32IDZFH-LABEL: fcvt_s_h: 382; RV32IDZFH: # %bb.0: 383; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0 384; RV32IDZFH-NEXT: ret 385; 386; RV64IZFH-LABEL: fcvt_s_h: 387; RV64IZFH: # %bb.0: 388; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 389; RV64IZFH-NEXT: ret 390; 391; RV64IDZFH-LABEL: fcvt_s_h: 392; RV64IDZFH: # %bb.0: 393; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0 394; RV64IDZFH-NEXT: ret 395 %1 = fpext half %a to float 396 ret float %1 397} 398 399define half @fcvt_h_d(double %a) nounwind { 400; RV32IZFH-LABEL: fcvt_h_d: 401; RV32IZFH: # %bb.0: 402; RV32IZFH-NEXT: addi sp, sp, -16 403; RV32IZFH-NEXT: sw ra, 12(sp) 404; RV32IZFH-NEXT: call __truncdfhf2 405; RV32IZFH-NEXT: lw ra, 12(sp) 406; RV32IZFH-NEXT: addi sp, sp, 16 407; RV32IZFH-NEXT: ret 408; 409; RV32IDZFH-LABEL: fcvt_h_d: 410; RV32IDZFH: # %bb.0: 411; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0 412; RV32IDZFH-NEXT: ret 413; 414; RV64IZFH-LABEL: fcvt_h_d: 415; RV64IZFH: # %bb.0: 416; RV64IZFH-NEXT: addi sp, sp, -16 417; RV64IZFH-NEXT: sd ra, 8(sp) 418; RV64IZFH-NEXT: call __truncdfhf2 419; RV64IZFH-NEXT: ld ra, 8(sp) 420; RV64IZFH-NEXT: addi sp, sp, 16 421; RV64IZFH-NEXT: ret 422; 423; RV64IDZFH-LABEL: fcvt_h_d: 424; RV64IDZFH: # %bb.0: 425; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0 426; RV64IDZFH-NEXT: ret 427 %1 = fptrunc double %a to half 428 ret half %1 429} 430 431define double @fcvt_d_h(half %a) nounwind { 432; RV32IZFH-LABEL: fcvt_d_h: 433; RV32IZFH: # %bb.0: 434; RV32IZFH-NEXT: addi sp, sp, -16 435; RV32IZFH-NEXT: sw ra, 12(sp) 436; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 437; RV32IZFH-NEXT: call __extendsfdf2 438; RV32IZFH-NEXT: lw ra, 12(sp) 439; RV32IZFH-NEXT: addi sp, sp, 16 440; RV32IZFH-NEXT: ret 441; 442; RV32IDZFH-LABEL: fcvt_d_h: 443; RV32IDZFH: # %bb.0: 444; RV32IDZFH-NEXT: fcvt.d.h fa0, fa0 445; RV32IDZFH-NEXT: ret 446; 447; RV64IZFH-LABEL: fcvt_d_h: 448; RV64IZFH: # %bb.0: 449; RV64IZFH-NEXT: addi sp, sp, -16 450; RV64IZFH-NEXT: sd ra, 8(sp) 451; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 452; RV64IZFH-NEXT: call __extendsfdf2 453; RV64IZFH-NEXT: ld ra, 8(sp) 454; RV64IZFH-NEXT: addi sp, sp, 16 455; RV64IZFH-NEXT: ret 456; 457; RV64IDZFH-LABEL: fcvt_d_h: 458; RV64IDZFH: # %bb.0: 459; RV64IDZFH-NEXT: fcvt.d.h fa0, fa0 460; RV64IDZFH-NEXT: ret 461 %1 = fpext half %a to double 462 ret double %1 463} 464 465define half @bitcast_h_i16(i16 %a) nounwind { 466; RV32IZFH-LABEL: bitcast_h_i16: 467; RV32IZFH: # %bb.0: 468; RV32IZFH-NEXT: fmv.h.x fa0, a0 469; RV32IZFH-NEXT: ret 470; 471; RV32IDZFH-LABEL: bitcast_h_i16: 472; RV32IDZFH: # %bb.0: 473; RV32IDZFH-NEXT: fmv.h.x fa0, a0 474; RV32IDZFH-NEXT: ret 475; 476; RV64IZFH-LABEL: bitcast_h_i16: 477; RV64IZFH: # %bb.0: 478; RV64IZFH-NEXT: fmv.h.x fa0, a0 479; RV64IZFH-NEXT: ret 480; 481; RV64IDZFH-LABEL: bitcast_h_i16: 482; RV64IDZFH: # %bb.0: 483; RV64IDZFH-NEXT: fmv.h.x fa0, a0 484; RV64IDZFH-NEXT: ret 485 %1 = bitcast i16 %a to half 486 ret half %1 487} 488 489define i16 @bitcast_i16_h(half %a) nounwind { 490; RV32IZFH-LABEL: bitcast_i16_h: 491; RV32IZFH: # %bb.0: 492; RV32IZFH-NEXT: fmv.x.h a0, fa0 493; RV32IZFH-NEXT: ret 494; 495; RV32IDZFH-LABEL: bitcast_i16_h: 496; RV32IDZFH: # %bb.0: 497; RV32IDZFH-NEXT: fmv.x.h a0, fa0 498; RV32IDZFH-NEXT: ret 499; 500; RV64IZFH-LABEL: bitcast_i16_h: 501; RV64IZFH: # %bb.0: 502; RV64IZFH-NEXT: fmv.x.h a0, fa0 503; RV64IZFH-NEXT: ret 504; 505; RV64IDZFH-LABEL: bitcast_i16_h: 506; RV64IDZFH: # %bb.0: 507; RV64IDZFH-NEXT: fmv.x.h a0, fa0 508; RV64IDZFH-NEXT: ret 509 %1 = bitcast half %a to i16 510 ret i16 %1 511} 512