1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ 3; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s 4; RUN: llc -mtriple=riscv32 -mattr=+d -mattr=+experimental-zfh -verify-machineinstrs \ 5; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s 6; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ 7; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s 8; RUN: llc -mtriple=riscv64 -mattr=+d -mattr=+experimental-zfh -verify-machineinstrs \ 9; RUN: -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s 10 11declare half @llvm.sqrt.f16(half) 12 13define half @sqrt_f16(half %a) nounwind { 14; RV32IZFH-LABEL: sqrt_f16: 15; RV32IZFH: # %bb.0: 16; RV32IZFH-NEXT: fsqrt.h fa0, fa0 17; RV32IZFH-NEXT: ret 18; 19; RV32IDZFH-LABEL: sqrt_f16: 20; RV32IDZFH: # %bb.0: 21; RV32IDZFH-NEXT: fsqrt.h fa0, fa0 22; RV32IDZFH-NEXT: ret 23; 24; RV64IZFH-LABEL: sqrt_f16: 25; RV64IZFH: # %bb.0: 26; RV64IZFH-NEXT: fsqrt.h fa0, fa0 27; RV64IZFH-NEXT: ret 28; 29; RV64IDZFH-LABEL: sqrt_f16: 30; RV64IDZFH: # %bb.0: 31; RV64IDZFH-NEXT: fsqrt.h fa0, fa0 32; RV64IDZFH-NEXT: ret 33 %1 = call half @llvm.sqrt.f16(half %a) 34 ret half %1 35} 36 37declare half @llvm.fma.f16(half, half, half) 38 39define half @fma_f16(half %a, half %b, half %c) nounwind { 40; RV32IZFH-LABEL: fma_f16: 41; RV32IZFH: # %bb.0: 42; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2 43; RV32IZFH-NEXT: ret 44; 45; RV32IDZFH-LABEL: fma_f16: 46; RV32IDZFH: # %bb.0: 47; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2 48; RV32IDZFH-NEXT: ret 49; 50; RV64IZFH-LABEL: fma_f16: 51; RV64IZFH: # %bb.0: 52; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2 53; RV64IZFH-NEXT: ret 54; 55; RV64IDZFH-LABEL: fma_f16: 56; RV64IDZFH: # %bb.0: 57; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2 58; RV64IDZFH-NEXT: ret 59 %1 = call half @llvm.fma.f16(half %a, half %b, half %c) 60 ret half %1 61} 62 63declare half @llvm.fmuladd.f16(half, half, half) 64 65define half @fmuladd_f16(half %a, half %b, half %c) nounwind { 66; RV32IZFH-LABEL: fmuladd_f16: 67; RV32IZFH: # %bb.0: 68; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2 69; RV32IZFH-NEXT: ret 70; 71; RV32IDZFH-LABEL: fmuladd_f16: 72; RV32IDZFH: # %bb.0: 73; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2 74; RV32IDZFH-NEXT: ret 75; 76; RV64IZFH-LABEL: fmuladd_f16: 77; RV64IZFH: # %bb.0: 78; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2 79; RV64IZFH-NEXT: ret 80; 81; RV64IDZFH-LABEL: fmuladd_f16: 82; RV64IDZFH: # %bb.0: 83; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2 84; RV64IDZFH-NEXT: ret 85 %1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c) 86 ret half %1 87} 88 89declare half @llvm.fabs.f16(half) 90 91define half @fabs_f16(half %a) nounwind { 92; RV32IZFH-LABEL: fabs_f16: 93; RV32IZFH: # %bb.0: 94; RV32IZFH-NEXT: fabs.h fa0, fa0 95; RV32IZFH-NEXT: ret 96; 97; RV32IDZFH-LABEL: fabs_f16: 98; RV32IDZFH: # %bb.0: 99; RV32IDZFH-NEXT: fabs.h fa0, fa0 100; RV32IDZFH-NEXT: ret 101; 102; RV64IZFH-LABEL: fabs_f16: 103; RV64IZFH: # %bb.0: 104; RV64IZFH-NEXT: fabs.h fa0, fa0 105; RV64IZFH-NEXT: ret 106; 107; RV64IDZFH-LABEL: fabs_f16: 108; RV64IDZFH: # %bb.0: 109; RV64IDZFH-NEXT: fabs.h fa0, fa0 110; RV64IDZFH-NEXT: ret 111 %1 = call half @llvm.fabs.f16(half %a) 112 ret half %1 113} 114 115declare half @llvm.minnum.f16(half, half) 116 117define half @minnum_f16(half %a, half %b) nounwind { 118; RV32IZFH-LABEL: minnum_f16: 119; RV32IZFH: # %bb.0: 120; RV32IZFH-NEXT: fmin.h fa0, fa0, fa1 121; RV32IZFH-NEXT: ret 122; 123; RV32IDZFH-LABEL: minnum_f16: 124; RV32IDZFH: # %bb.0: 125; RV32IDZFH-NEXT: fmin.h fa0, fa0, fa1 126; RV32IDZFH-NEXT: ret 127; 128; RV64IZFH-LABEL: minnum_f16: 129; RV64IZFH: # %bb.0: 130; RV64IZFH-NEXT: fmin.h fa0, fa0, fa1 131; RV64IZFH-NEXT: ret 132; 133; RV64IDZFH-LABEL: minnum_f16: 134; RV64IDZFH: # %bb.0: 135; RV64IDZFH-NEXT: fmin.h fa0, fa0, fa1 136; RV64IDZFH-NEXT: ret 137 %1 = call half @llvm.minnum.f16(half %a, half %b) 138 ret half %1 139} 140 141declare half @llvm.maxnum.f16(half, half) 142 143define half @maxnum_f16(half %a, half %b) nounwind { 144; RV32IZFH-LABEL: maxnum_f16: 145; RV32IZFH: # %bb.0: 146; RV32IZFH-NEXT: fmax.h fa0, fa0, fa1 147; RV32IZFH-NEXT: ret 148; 149; RV32IDZFH-LABEL: maxnum_f16: 150; RV32IDZFH: # %bb.0: 151; RV32IDZFH-NEXT: fmax.h fa0, fa0, fa1 152; RV32IDZFH-NEXT: ret 153; 154; RV64IZFH-LABEL: maxnum_f16: 155; RV64IZFH: # %bb.0: 156; RV64IZFH-NEXT: fmax.h fa0, fa0, fa1 157; RV64IZFH-NEXT: ret 158; 159; RV64IDZFH-LABEL: maxnum_f16: 160; RV64IDZFH: # %bb.0: 161; RV64IDZFH-NEXT: fmax.h fa0, fa0, fa1 162; RV64IDZFH-NEXT: ret 163 %1 = call half @llvm.maxnum.f16(half %a, half %b) 164 ret half %1 165} 166 167declare half @llvm.copysign.f16(half, half) 168 169define half @copysign_f16(half %a, half %b) nounwind { 170; RV32IZFH-LABEL: copysign_f16: 171; RV32IZFH: # %bb.0: 172; RV32IZFH-NEXT: fsgnj.h fa0, fa0, fa1 173; RV32IZFH-NEXT: ret 174; 175; RV32IDZFH-LABEL: copysign_f16: 176; RV32IDZFH: # %bb.0: 177; RV32IDZFH-NEXT: fsgnj.h fa0, fa0, fa1 178; RV32IDZFH-NEXT: ret 179; 180; RV64IZFH-LABEL: copysign_f16: 181; RV64IZFH: # %bb.0: 182; RV64IZFH-NEXT: fsgnj.h fa0, fa0, fa1 183; RV64IZFH-NEXT: ret 184; 185; RV64IDZFH-LABEL: copysign_f16: 186; RV64IDZFH: # %bb.0: 187; RV64IDZFH-NEXT: fsgnj.h fa0, fa0, fa1 188; RV64IDZFH-NEXT: ret 189 %1 = call half @llvm.copysign.f16(half %a, half %b) 190 ret half %1 191} 192