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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV32IB
6; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs -verify-machineinstrs < %s \
7; RUN:   | FileCheck %s -check-prefix=RV32IBS
8
9define i32 @sbclr_i32(i32 %a, i32 %b) nounwind {
10; RV32I-LABEL: sbclr_i32:
11; RV32I:       # %bb.0:
12; RV32I-NEXT:    addi a2, zero, 1
13; RV32I-NEXT:    sll a1, a2, a1
14; RV32I-NEXT:    not a1, a1
15; RV32I-NEXT:    and a0, a1, a0
16; RV32I-NEXT:    ret
17;
18; RV32IB-LABEL: sbclr_i32:
19; RV32IB:       # %bb.0:
20; RV32IB-NEXT:    sbclr a0, a0, a1
21; RV32IB-NEXT:    ret
22;
23; RV32IBS-LABEL: sbclr_i32:
24; RV32IBS:       # %bb.0:
25; RV32IBS-NEXT:    sbclr a0, a0, a1
26; RV32IBS-NEXT:    ret
27  %and = and i32 %b, 31
28  %shl = shl nuw i32 1, %and
29  %neg = xor i32 %shl, -1
30  %and1 = and i32 %neg, %a
31  ret i32 %and1
32}
33
34define i32 @sbclr_i32_no_mask(i32 %a, i32 %b) nounwind {
35; RV32I-LABEL: sbclr_i32_no_mask:
36; RV32I:       # %bb.0:
37; RV32I-NEXT:    addi a2, zero, 1
38; RV32I-NEXT:    sll a1, a2, a1
39; RV32I-NEXT:    not a1, a1
40; RV32I-NEXT:    and a0, a1, a0
41; RV32I-NEXT:    ret
42;
43; RV32IB-LABEL: sbclr_i32_no_mask:
44; RV32IB:       # %bb.0:
45; RV32IB-NEXT:    sbclr a0, a0, a1
46; RV32IB-NEXT:    ret
47;
48; RV32IBS-LABEL: sbclr_i32_no_mask:
49; RV32IBS:       # %bb.0:
50; RV32IBS-NEXT:    sbclr a0, a0, a1
51; RV32IBS-NEXT:    ret
52  %shl = shl nuw i32 1, %b
53  %neg = xor i32 %shl, -1
54  %and1 = and i32 %neg, %a
55  ret i32 %and1
56}
57
58define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
59; RV32I-LABEL: sbclr_i64:
60; RV32I:       # %bb.0:
61; RV32I-NEXT:    andi a3, a2, 63
62; RV32I-NEXT:    addi a4, a3, -32
63; RV32I-NEXT:    addi a3, zero, 1
64; RV32I-NEXT:    bltz a4, .LBB2_2
65; RV32I-NEXT:  # %bb.1:
66; RV32I-NEXT:    mv a2, zero
67; RV32I-NEXT:    sll a4, a3, a4
68; RV32I-NEXT:    j .LBB2_3
69; RV32I-NEXT:  .LBB2_2:
70; RV32I-NEXT:    mv a4, zero
71; RV32I-NEXT:    sll a2, a3, a2
72; RV32I-NEXT:  .LBB2_3:
73; RV32I-NEXT:    not a3, a4
74; RV32I-NEXT:    not a2, a2
75; RV32I-NEXT:    and a0, a2, a0
76; RV32I-NEXT:    and a1, a3, a1
77; RV32I-NEXT:    ret
78;
79; RV32IB-LABEL: sbclr_i64:
80; RV32IB:       # %bb.0:
81; RV32IB-NEXT:    andi a3, a2, 63
82; RV32IB-NEXT:    addi a3, a3, -32
83; RV32IB-NEXT:    bltz a3, .LBB2_2
84; RV32IB-NEXT:  # %bb.1:
85; RV32IB-NEXT:    mv a2, zero
86; RV32IB-NEXT:    sbset a3, zero, a3
87; RV32IB-NEXT:    j .LBB2_3
88; RV32IB-NEXT:  .LBB2_2:
89; RV32IB-NEXT:    mv a3, zero
90; RV32IB-NEXT:    sbset a2, zero, a2
91; RV32IB-NEXT:  .LBB2_3:
92; RV32IB-NEXT:    andn a0, a0, a2
93; RV32IB-NEXT:    andn a1, a1, a3
94; RV32IB-NEXT:    ret
95;
96; RV32IBS-LABEL: sbclr_i64:
97; RV32IBS:       # %bb.0:
98; RV32IBS-NEXT:    andi a3, a2, 63
99; RV32IBS-NEXT:    addi a3, a3, -32
100; RV32IBS-NEXT:    bltz a3, .LBB2_2
101; RV32IBS-NEXT:  # %bb.1:
102; RV32IBS-NEXT:    mv a2, zero
103; RV32IBS-NEXT:    sbset a3, zero, a3
104; RV32IBS-NEXT:    j .LBB2_3
105; RV32IBS-NEXT:  .LBB2_2:
106; RV32IBS-NEXT:    mv a3, zero
107; RV32IBS-NEXT:    sbset a2, zero, a2
108; RV32IBS-NEXT:  .LBB2_3:
109; RV32IBS-NEXT:    not a3, a3
110; RV32IBS-NEXT:    not a2, a2
111; RV32IBS-NEXT:    and a0, a2, a0
112; RV32IBS-NEXT:    and a1, a3, a1
113; RV32IBS-NEXT:    ret
114  %and = and i64 %b, 63
115  %shl = shl nuw i64 1, %and
116  %neg = xor i64 %shl, -1
117  %and1 = and i64 %neg, %a
118  ret i64 %and1
119}
120
121define i32 @sbset_i32(i32 %a, i32 %b) nounwind {
122; RV32I-LABEL: sbset_i32:
123; RV32I:       # %bb.0:
124; RV32I-NEXT:    addi a2, zero, 1
125; RV32I-NEXT:    sll a1, a2, a1
126; RV32I-NEXT:    or a0, a1, a0
127; RV32I-NEXT:    ret
128;
129; RV32IB-LABEL: sbset_i32:
130; RV32IB:       # %bb.0:
131; RV32IB-NEXT:    sbset a0, a0, a1
132; RV32IB-NEXT:    ret
133;
134; RV32IBS-LABEL: sbset_i32:
135; RV32IBS:       # %bb.0:
136; RV32IBS-NEXT:    sbset a0, a0, a1
137; RV32IBS-NEXT:    ret
138  %and = and i32 %b, 31
139  %shl = shl nuw i32 1, %and
140  %or = or i32 %shl, %a
141  ret i32 %or
142}
143
144define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind {
145; RV32I-LABEL: sbset_i32_no_mask:
146; RV32I:       # %bb.0:
147; RV32I-NEXT:    addi a2, zero, 1
148; RV32I-NEXT:    sll a1, a2, a1
149; RV32I-NEXT:    or a0, a1, a0
150; RV32I-NEXT:    ret
151;
152; RV32IB-LABEL: sbset_i32_no_mask:
153; RV32IB:       # %bb.0:
154; RV32IB-NEXT:    sbset a0, a0, a1
155; RV32IB-NEXT:    ret
156;
157; RV32IBS-LABEL: sbset_i32_no_mask:
158; RV32IBS:       # %bb.0:
159; RV32IBS-NEXT:    sbset a0, a0, a1
160; RV32IBS-NEXT:    ret
161  %shl = shl nuw i32 1, %b
162  %or = or i32 %shl, %a
163  ret i32 %or
164}
165
166; We can use sbsetw for 1 << x by setting the first source to zero.
167define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
168; RV32I-LABEL: sbset_i32_zero:
169; RV32I:       # %bb.0:
170; RV32I-NEXT:    addi a1, zero, 1
171; RV32I-NEXT:    sll a0, a1, a0
172; RV32I-NEXT:    ret
173;
174; RV32IB-LABEL: sbset_i32_zero:
175; RV32IB:       # %bb.0:
176; RV32IB-NEXT:    sbset a0, zero, a0
177; RV32IB-NEXT:    ret
178;
179; RV32IBS-LABEL: sbset_i32_zero:
180; RV32IBS:       # %bb.0:
181; RV32IBS-NEXT:    sbset a0, zero, a0
182; RV32IBS-NEXT:    ret
183  %shl = shl i32 1, %a
184  ret i32 %shl
185}
186
187; As we are not matching directly i64 code patterns on RV32 some i64 patterns
188; don't have yet any matching bit manipulation instructions on RV32.
189; This test is presented here in case future expansions of the experimental-b
190; extension introduce instructions suitable for this pattern.
191
192define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
193; RV32I-LABEL: sbset_i64:
194; RV32I:       # %bb.0:
195; RV32I-NEXT:    addi a3, zero, 1
196; RV32I-NEXT:    sll a2, a3, a2
197; RV32I-NEXT:    srai a3, a2, 31
198; RV32I-NEXT:    or a0, a2, a0
199; RV32I-NEXT:    or a1, a3, a1
200; RV32I-NEXT:    ret
201;
202; RV32IB-LABEL: sbset_i64:
203; RV32IB:       # %bb.0:
204; RV32IB-NEXT:    sbset a3, zero, a2
205; RV32IB-NEXT:    srai a3, a3, 31
206; RV32IB-NEXT:    sbset a0, a0, a2
207; RV32IB-NEXT:    or a1, a3, a1
208; RV32IB-NEXT:    ret
209;
210; RV32IBS-LABEL: sbset_i64:
211; RV32IBS:       # %bb.0:
212; RV32IBS-NEXT:    sbset a3, zero, a2
213; RV32IBS-NEXT:    srai a3, a3, 31
214; RV32IBS-NEXT:    sbset a0, a0, a2
215; RV32IBS-NEXT:    or a1, a3, a1
216; RV32IBS-NEXT:    ret
217  %1 = trunc i64 %b to i32
218  %conv = and i32 %1, 63
219  %shl = shl nuw i32 1, %conv
220  %conv1 = sext i32 %shl to i64
221  %or = or i64 %conv1, %a
222  ret i64 %or
223}
224
225define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
226; RV32I-LABEL: sbset_i64_zero:
227; RV32I:       # %bb.0:
228; RV32I-NEXT:    addi a1, a0, -32
229; RV32I-NEXT:    addi a2, zero, 1
230; RV32I-NEXT:    bltz a1, .LBB7_2
231; RV32I-NEXT:  # %bb.1:
232; RV32I-NEXT:    mv a0, zero
233; RV32I-NEXT:    sll a1, a2, a1
234; RV32I-NEXT:    ret
235; RV32I-NEXT:  .LBB7_2:
236; RV32I-NEXT:    mv a1, zero
237; RV32I-NEXT:    sll a0, a2, a0
238; RV32I-NEXT:    ret
239;
240; RV32IB-LABEL: sbset_i64_zero:
241; RV32IB:       # %bb.0:
242; RV32IB-NEXT:    addi a1, a0, -32
243; RV32IB-NEXT:    bltz a1, .LBB7_2
244; RV32IB-NEXT:  # %bb.1:
245; RV32IB-NEXT:    mv a0, zero
246; RV32IB-NEXT:    sbset a1, zero, a1
247; RV32IB-NEXT:    ret
248; RV32IB-NEXT:  .LBB7_2:
249; RV32IB-NEXT:    mv a1, zero
250; RV32IB-NEXT:    sbset a0, zero, a0
251; RV32IB-NEXT:    ret
252;
253; RV32IBS-LABEL: sbset_i64_zero:
254; RV32IBS:       # %bb.0:
255; RV32IBS-NEXT:    addi a1, a0, -32
256; RV32IBS-NEXT:    bltz a1, .LBB7_2
257; RV32IBS-NEXT:  # %bb.1:
258; RV32IBS-NEXT:    mv a0, zero
259; RV32IBS-NEXT:    sbset a1, zero, a1
260; RV32IBS-NEXT:    ret
261; RV32IBS-NEXT:  .LBB7_2:
262; RV32IBS-NEXT:    mv a1, zero
263; RV32IBS-NEXT:    sbset a0, zero, a0
264; RV32IBS-NEXT:    ret
265  %shl = shl i64 1, %a
266  ret i64 %shl
267}
268
269define i32 @sbinv_i32(i32 %a, i32 %b) nounwind {
270; RV32I-LABEL: sbinv_i32:
271; RV32I:       # %bb.0:
272; RV32I-NEXT:    addi a2, zero, 1
273; RV32I-NEXT:    sll a1, a2, a1
274; RV32I-NEXT:    xor a0, a1, a0
275; RV32I-NEXT:    ret
276;
277; RV32IB-LABEL: sbinv_i32:
278; RV32IB:       # %bb.0:
279; RV32IB-NEXT:    sbinv a0, a0, a1
280; RV32IB-NEXT:    ret
281;
282; RV32IBS-LABEL: sbinv_i32:
283; RV32IBS:       # %bb.0:
284; RV32IBS-NEXT:    sbinv a0, a0, a1
285; RV32IBS-NEXT:    ret
286  %and = and i32 %b, 31
287  %shl = shl nuw i32 1, %and
288  %xor = xor i32 %shl, %a
289  ret i32 %xor
290}
291
292; As we are not matching directly i64 code patterns on RV32 some i64 patterns
293; don't have yet any matching bit manipulation instructions on RV32.
294; This test is presented here in case future expansions of the experimental-b
295; extension introduce instructions suitable for this pattern.
296
297define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
298; RV32I-LABEL: sbinv_i64:
299; RV32I:       # %bb.0:
300; RV32I-NEXT:    addi a3, zero, 1
301; RV32I-NEXT:    sll a2, a3, a2
302; RV32I-NEXT:    srai a3, a2, 31
303; RV32I-NEXT:    xor a0, a2, a0
304; RV32I-NEXT:    xor a1, a3, a1
305; RV32I-NEXT:    ret
306;
307; RV32IB-LABEL: sbinv_i64:
308; RV32IB:       # %bb.0:
309; RV32IB-NEXT:    sbset a3, zero, a2
310; RV32IB-NEXT:    srai a3, a3, 31
311; RV32IB-NEXT:    sbinv a0, a0, a2
312; RV32IB-NEXT:    xor a1, a3, a1
313; RV32IB-NEXT:    ret
314;
315; RV32IBS-LABEL: sbinv_i64:
316; RV32IBS:       # %bb.0:
317; RV32IBS-NEXT:    sbset a3, zero, a2
318; RV32IBS-NEXT:    srai a3, a3, 31
319; RV32IBS-NEXT:    sbinv a0, a0, a2
320; RV32IBS-NEXT:    xor a1, a3, a1
321; RV32IBS-NEXT:    ret
322  %1 = trunc i64 %b to i32
323  %conv = and i32 %1, 63
324  %shl = shl nuw i32 1, %conv
325  %conv1 = sext i32 %shl to i64
326  %xor = xor i64 %conv1, %a
327  ret i64 %xor
328}
329
330define i32 @sbext_i32(i32 %a, i32 %b) nounwind {
331; RV32I-LABEL: sbext_i32:
332; RV32I:       # %bb.0:
333; RV32I-NEXT:    srl a0, a0, a1
334; RV32I-NEXT:    andi a0, a0, 1
335; RV32I-NEXT:    ret
336;
337; RV32IB-LABEL: sbext_i32:
338; RV32IB:       # %bb.0:
339; RV32IB-NEXT:    sbext a0, a0, a1
340; RV32IB-NEXT:    ret
341;
342; RV32IBS-LABEL: sbext_i32:
343; RV32IBS:       # %bb.0:
344; RV32IBS-NEXT:    sbext a0, a0, a1
345; RV32IBS-NEXT:    ret
346  %and = and i32 %b, 31
347  %shr = lshr i32 %a, %and
348  %and1 = and i32 %shr, 1
349  ret i32 %and1
350}
351
352define i32 @sbext_i32_no_mask(i32 %a, i32 %b) nounwind {
353; RV32I-LABEL: sbext_i32_no_mask:
354; RV32I:       # %bb.0:
355; RV32I-NEXT:    srl a0, a0, a1
356; RV32I-NEXT:    andi a0, a0, 1
357; RV32I-NEXT:    ret
358;
359; RV32IB-LABEL: sbext_i32_no_mask:
360; RV32IB:       # %bb.0:
361; RV32IB-NEXT:    sbext a0, a0, a1
362; RV32IB-NEXT:    ret
363;
364; RV32IBS-LABEL: sbext_i32_no_mask:
365; RV32IBS:       # %bb.0:
366; RV32IBS-NEXT:    sbext a0, a0, a1
367; RV32IBS-NEXT:    ret
368  %shr = lshr i32 %a, %b
369  %and1 = and i32 %shr, 1
370  ret i32 %and1
371}
372
373; As we are not matching directly i64 code patterns on RV32 some i64 patterns
374; don't have yet any matching bit manipulation instructions on RV32.
375; This test is presented here in case future expansions of the experimental-b
376; extension introduce instructions suitable for this pattern.
377
378define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
379; RV32I-LABEL: sbext_i64:
380; RV32I:       # %bb.0:
381; RV32I-NEXT:    andi a3, a2, 63
382; RV32I-NEXT:    addi a4, a3, -32
383; RV32I-NEXT:    bltz a4, .LBB12_2
384; RV32I-NEXT:  # %bb.1:
385; RV32I-NEXT:    srl a0, a1, a4
386; RV32I-NEXT:    j .LBB12_3
387; RV32I-NEXT:  .LBB12_2:
388; RV32I-NEXT:    srl a0, a0, a2
389; RV32I-NEXT:    addi a2, zero, 31
390; RV32I-NEXT:    sub a2, a2, a3
391; RV32I-NEXT:    slli a1, a1, 1
392; RV32I-NEXT:    sll a1, a1, a2
393; RV32I-NEXT:    or a0, a0, a1
394; RV32I-NEXT:  .LBB12_3:
395; RV32I-NEXT:    andi a0, a0, 1
396; RV32I-NEXT:    mv a1, zero
397; RV32I-NEXT:    ret
398;
399; RV32IB-LABEL: sbext_i64:
400; RV32IB:       # %bb.0:
401; RV32IB-NEXT:    andi a3, a2, 63
402; RV32IB-NEXT:    addi a4, a3, -32
403; RV32IB-NEXT:    bltz a4, .LBB12_2
404; RV32IB-NEXT:  # %bb.1:
405; RV32IB-NEXT:    srl a0, a1, a4
406; RV32IB-NEXT:    j .LBB12_3
407; RV32IB-NEXT:  .LBB12_2:
408; RV32IB-NEXT:    srl a0, a0, a2
409; RV32IB-NEXT:    addi a2, zero, 31
410; RV32IB-NEXT:    sub a2, a2, a3
411; RV32IB-NEXT:    slli a1, a1, 1
412; RV32IB-NEXT:    sll a1, a1, a2
413; RV32IB-NEXT:    or a0, a0, a1
414; RV32IB-NEXT:  .LBB12_3:
415; RV32IB-NEXT:    andi a0, a0, 1
416; RV32IB-NEXT:    mv a1, zero
417; RV32IB-NEXT:    ret
418;
419; RV32IBS-LABEL: sbext_i64:
420; RV32IBS:       # %bb.0:
421; RV32IBS-NEXT:    andi a3, a2, 63
422; RV32IBS-NEXT:    addi a4, a3, -32
423; RV32IBS-NEXT:    bltz a4, .LBB12_2
424; RV32IBS-NEXT:  # %bb.1:
425; RV32IBS-NEXT:    srl a0, a1, a4
426; RV32IBS-NEXT:    j .LBB12_3
427; RV32IBS-NEXT:  .LBB12_2:
428; RV32IBS-NEXT:    srl a0, a0, a2
429; RV32IBS-NEXT:    addi a2, zero, 31
430; RV32IBS-NEXT:    sub a2, a2, a3
431; RV32IBS-NEXT:    slli a1, a1, 1
432; RV32IBS-NEXT:    sll a1, a1, a2
433; RV32IBS-NEXT:    or a0, a0, a1
434; RV32IBS-NEXT:  .LBB12_3:
435; RV32IBS-NEXT:    andi a0, a0, 1
436; RV32IBS-NEXT:    mv a1, zero
437; RV32IBS-NEXT:    ret
438  %conv = and i64 %b, 63
439  %shr = lshr i64 %a, %conv
440  %and1 = and i64 %shr, 1
441  ret i64 %and1
442}
443
444define i32 @sbexti_i32(i32 %a) nounwind {
445; RV32I-LABEL: sbexti_i32:
446; RV32I:       # %bb.0:
447; RV32I-NEXT:    srli a0, a0, 5
448; RV32I-NEXT:    andi a0, a0, 1
449; RV32I-NEXT:    ret
450;
451; RV32IB-LABEL: sbexti_i32:
452; RV32IB:       # %bb.0:
453; RV32IB-NEXT:    sbexti a0, a0, 5
454; RV32IB-NEXT:    ret
455;
456; RV32IBS-LABEL: sbexti_i32:
457; RV32IBS:       # %bb.0:
458; RV32IBS-NEXT:    sbexti a0, a0, 5
459; RV32IBS-NEXT:    ret
460  %shr = lshr i32 %a, 5
461  %and = and i32 %shr, 1
462  ret i32 %and
463}
464
465define i64 @sbexti_i64(i64 %a) nounwind {
466; RV32I-LABEL: sbexti_i64:
467; RV32I:       # %bb.0:
468; RV32I-NEXT:    srli a0, a0, 5
469; RV32I-NEXT:    andi a0, a0, 1
470; RV32I-NEXT:    mv a1, zero
471; RV32I-NEXT:    ret
472;
473; RV32IB-LABEL: sbexti_i64:
474; RV32IB:       # %bb.0:
475; RV32IB-NEXT:    sbexti a0, a0, 5
476; RV32IB-NEXT:    mv a1, zero
477; RV32IB-NEXT:    ret
478;
479; RV32IBS-LABEL: sbexti_i64:
480; RV32IBS:       # %bb.0:
481; RV32IBS-NEXT:    sbexti a0, a0, 5
482; RV32IBS-NEXT:    mv a1, zero
483; RV32IBS-NEXT:    ret
484  %shr = lshr i64 %a, 5
485  %and = and i64 %shr, 1
486  ret i64 %and
487}
488
489define i32 @sbclri_i32_10(i32 %a) nounwind {
490; RV32I-LABEL: sbclri_i32_10:
491; RV32I:       # %bb.0:
492; RV32I-NEXT:    andi a0, a0, -1025
493; RV32I-NEXT:    ret
494;
495; RV32IB-LABEL: sbclri_i32_10:
496; RV32IB:       # %bb.0:
497; RV32IB-NEXT:    andi a0, a0, -1025
498; RV32IB-NEXT:    ret
499;
500; RV32IBS-LABEL: sbclri_i32_10:
501; RV32IBS:       # %bb.0:
502; RV32IBS-NEXT:    andi a0, a0, -1025
503; RV32IBS-NEXT:    ret
504  %and = and i32 %a, -1025
505  ret i32 %and
506}
507
508define i32 @sbclri_i32_11(i32 %a) nounwind {
509; RV32I-LABEL: sbclri_i32_11:
510; RV32I:       # %bb.0:
511; RV32I-NEXT:    lui a1, 1048575
512; RV32I-NEXT:    addi a1, a1, 2047
513; RV32I-NEXT:    and a0, a0, a1
514; RV32I-NEXT:    ret
515;
516; RV32IB-LABEL: sbclri_i32_11:
517; RV32IB:       # %bb.0:
518; RV32IB-NEXT:    sbclri a0, a0, 11
519; RV32IB-NEXT:    ret
520;
521; RV32IBS-LABEL: sbclri_i32_11:
522; RV32IBS:       # %bb.0:
523; RV32IBS-NEXT:    sbclri a0, a0, 11
524; RV32IBS-NEXT:    ret
525  %and = and i32 %a, -2049
526  ret i32 %and
527}
528
529define i32 @sbclri_i32_30(i32 %a) nounwind {
530; RV32I-LABEL: sbclri_i32_30:
531; RV32I:       # %bb.0:
532; RV32I-NEXT:    lui a1, 786432
533; RV32I-NEXT:    addi a1, a1, -1
534; RV32I-NEXT:    and a0, a0, a1
535; RV32I-NEXT:    ret
536;
537; RV32IB-LABEL: sbclri_i32_30:
538; RV32IB:       # %bb.0:
539; RV32IB-NEXT:    sbclri a0, a0, 30
540; RV32IB-NEXT:    ret
541;
542; RV32IBS-LABEL: sbclri_i32_30:
543; RV32IBS:       # %bb.0:
544; RV32IBS-NEXT:    sbclri a0, a0, 30
545; RV32IBS-NEXT:    ret
546  %and = and i32 %a, -1073741825
547  ret i32 %and
548}
549
550define i32 @sbclri_i32_31(i32 %a) nounwind {
551; RV32I-LABEL: sbclri_i32_31:
552; RV32I:       # %bb.0:
553; RV32I-NEXT:    lui a1, 524288
554; RV32I-NEXT:    addi a1, a1, -1
555; RV32I-NEXT:    and a0, a0, a1
556; RV32I-NEXT:    ret
557;
558; RV32IB-LABEL: sbclri_i32_31:
559; RV32IB:       # %bb.0:
560; RV32IB-NEXT:    sbclri a0, a0, 31
561; RV32IB-NEXT:    ret
562;
563; RV32IBS-LABEL: sbclri_i32_31:
564; RV32IBS:       # %bb.0:
565; RV32IBS-NEXT:    sbclri a0, a0, 31
566; RV32IBS-NEXT:    ret
567  %and = and i32 %a, -2147483649
568  ret i32 %and
569}
570
571define i32 @sbseti_i32_10(i32 %a) nounwind {
572; RV32I-LABEL: sbseti_i32_10:
573; RV32I:       # %bb.0:
574; RV32I-NEXT:    ori a0, a0, 1024
575; RV32I-NEXT:    ret
576;
577; RV32IB-LABEL: sbseti_i32_10:
578; RV32IB:       # %bb.0:
579; RV32IB-NEXT:    ori a0, a0, 1024
580; RV32IB-NEXT:    ret
581;
582; RV32IBS-LABEL: sbseti_i32_10:
583; RV32IBS:       # %bb.0:
584; RV32IBS-NEXT:    ori a0, a0, 1024
585; RV32IBS-NEXT:    ret
586  %or = or i32 %a, 1024
587  ret i32 %or
588}
589
590define i32 @sbseti_i32_11(i32 %a) nounwind {
591; RV32I-LABEL: sbseti_i32_11:
592; RV32I:       # %bb.0:
593; RV32I-NEXT:    lui a1, 1
594; RV32I-NEXT:    addi a1, a1, -2048
595; RV32I-NEXT:    or a0, a0, a1
596; RV32I-NEXT:    ret
597;
598; RV32IB-LABEL: sbseti_i32_11:
599; RV32IB:       # %bb.0:
600; RV32IB-NEXT:    sbseti a0, a0, 11
601; RV32IB-NEXT:    ret
602;
603; RV32IBS-LABEL: sbseti_i32_11:
604; RV32IBS:       # %bb.0:
605; RV32IBS-NEXT:    sbseti a0, a0, 11
606; RV32IBS-NEXT:    ret
607  %or = or i32 %a, 2048
608  ret i32 %or
609}
610
611define i32 @sbseti_i32_30(i32 %a) nounwind {
612; RV32I-LABEL: sbseti_i32_30:
613; RV32I:       # %bb.0:
614; RV32I-NEXT:    lui a1, 262144
615; RV32I-NEXT:    or a0, a0, a1
616; RV32I-NEXT:    ret
617;
618; RV32IB-LABEL: sbseti_i32_30:
619; RV32IB:       # %bb.0:
620; RV32IB-NEXT:    sbseti a0, a0, 30
621; RV32IB-NEXT:    ret
622;
623; RV32IBS-LABEL: sbseti_i32_30:
624; RV32IBS:       # %bb.0:
625; RV32IBS-NEXT:    sbseti a0, a0, 30
626; RV32IBS-NEXT:    ret
627  %or = or i32 %a, 1073741824
628  ret i32 %or
629}
630
631define i32 @sbseti_i32_31(i32 %a) nounwind {
632; RV32I-LABEL: sbseti_i32_31:
633; RV32I:       # %bb.0:
634; RV32I-NEXT:    lui a1, 524288
635; RV32I-NEXT:    or a0, a0, a1
636; RV32I-NEXT:    ret
637;
638; RV32IB-LABEL: sbseti_i32_31:
639; RV32IB:       # %bb.0:
640; RV32IB-NEXT:    sbseti a0, a0, 31
641; RV32IB-NEXT:    ret
642;
643; RV32IBS-LABEL: sbseti_i32_31:
644; RV32IBS:       # %bb.0:
645; RV32IBS-NEXT:    sbseti a0, a0, 31
646; RV32IBS-NEXT:    ret
647  %or = or i32 %a, 2147483648
648  ret i32 %or
649}
650
651define i32 @sbinvi_i32_10(i32 %a) nounwind {
652; RV32I-LABEL: sbinvi_i32_10:
653; RV32I:       # %bb.0:
654; RV32I-NEXT:    xori a0, a0, 1024
655; RV32I-NEXT:    ret
656;
657; RV32IB-LABEL: sbinvi_i32_10:
658; RV32IB:       # %bb.0:
659; RV32IB-NEXT:    xori a0, a0, 1024
660; RV32IB-NEXT:    ret
661;
662; RV32IBS-LABEL: sbinvi_i32_10:
663; RV32IBS:       # %bb.0:
664; RV32IBS-NEXT:    xori a0, a0, 1024
665; RV32IBS-NEXT:    ret
666  %xor = xor i32 %a, 1024
667  ret i32 %xor
668}
669
670define i32 @sbinvi_i32_11(i32 %a) nounwind {
671; RV32I-LABEL: sbinvi_i32_11:
672; RV32I:       # %bb.0:
673; RV32I-NEXT:    lui a1, 1
674; RV32I-NEXT:    addi a1, a1, -2048
675; RV32I-NEXT:    xor a0, a0, a1
676; RV32I-NEXT:    ret
677;
678; RV32IB-LABEL: sbinvi_i32_11:
679; RV32IB:       # %bb.0:
680; RV32IB-NEXT:    sbinvi a0, a0, 11
681; RV32IB-NEXT:    ret
682;
683; RV32IBS-LABEL: sbinvi_i32_11:
684; RV32IBS:       # %bb.0:
685; RV32IBS-NEXT:    sbinvi a0, a0, 11
686; RV32IBS-NEXT:    ret
687  %xor = xor i32 %a, 2048
688  ret i32 %xor
689}
690
691define i32 @sbinvi_i32_30(i32 %a) nounwind {
692; RV32I-LABEL: sbinvi_i32_30:
693; RV32I:       # %bb.0:
694; RV32I-NEXT:    lui a1, 262144
695; RV32I-NEXT:    xor a0, a0, a1
696; RV32I-NEXT:    ret
697;
698; RV32IB-LABEL: sbinvi_i32_30:
699; RV32IB:       # %bb.0:
700; RV32IB-NEXT:    sbinvi a0, a0, 30
701; RV32IB-NEXT:    ret
702;
703; RV32IBS-LABEL: sbinvi_i32_30:
704; RV32IBS:       # %bb.0:
705; RV32IBS-NEXT:    sbinvi a0, a0, 30
706; RV32IBS-NEXT:    ret
707  %xor = xor i32 %a, 1073741824
708  ret i32 %xor
709}
710
711define i32 @sbinvi_i32_31(i32 %a) nounwind {
712; RV32I-LABEL: sbinvi_i32_31:
713; RV32I:       # %bb.0:
714; RV32I-NEXT:    lui a1, 524288
715; RV32I-NEXT:    xor a0, a0, a1
716; RV32I-NEXT:    ret
717;
718; RV32IB-LABEL: sbinvi_i32_31:
719; RV32IB:       # %bb.0:
720; RV32IB-NEXT:    sbinvi a0, a0, 31
721; RV32IB-NEXT:    ret
722;
723; RV32IBS-LABEL: sbinvi_i32_31:
724; RV32IBS:       # %bb.0:
725; RV32IBS-NEXT:    sbinvi a0, a0, 31
726; RV32IBS-NEXT:    ret
727  %xor = xor i32 %a, 2147483648
728  ret i32 %xor
729}
730