1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV64ID 4 5; This file exhaustively checks double<->i32 conversions. In general, 6; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is 7; generated for an fpto[s|u]i conversion if the result doesn't fit in the 8; target type. 9 10define i32 @aext_fptosi(double %a) nounwind { 11; RV64ID-LABEL: aext_fptosi: 12; RV64ID: # %bb.0: 13; RV64ID-NEXT: fmv.d.x ft0, a0 14; RV64ID-NEXT: fcvt.l.d a0, ft0, rtz 15; RV64ID-NEXT: ret 16 %1 = fptosi double %a to i32 17 ret i32 %1 18} 19 20define signext i32 @sext_fptosi(double %a) nounwind { 21; RV64ID-LABEL: sext_fptosi: 22; RV64ID: # %bb.0: 23; RV64ID-NEXT: fmv.d.x ft0, a0 24; RV64ID-NEXT: fcvt.l.d a0, ft0, rtz 25; RV64ID-NEXT: ret 26 %1 = fptosi double %a to i32 27 ret i32 %1 28} 29 30define zeroext i32 @zext_fptosi(double %a) nounwind { 31; RV64ID-LABEL: zext_fptosi: 32; RV64ID: # %bb.0: 33; RV64ID-NEXT: fmv.d.x ft0, a0 34; RV64ID-NEXT: fcvt.l.d a0, ft0, rtz 35; RV64ID-NEXT: slli a0, a0, 32 36; RV64ID-NEXT: srli a0, a0, 32 37; RV64ID-NEXT: ret 38 %1 = fptosi double %a to i32 39 ret i32 %1 40} 41 42define i32 @aext_fptoui(double %a) nounwind { 43; RV64ID-LABEL: aext_fptoui: 44; RV64ID: # %bb.0: 45; RV64ID-NEXT: fmv.d.x ft0, a0 46; RV64ID-NEXT: fcvt.lu.d a0, ft0, rtz 47; RV64ID-NEXT: ret 48 %1 = fptoui double %a to i32 49 ret i32 %1 50} 51 52define signext i32 @sext_fptoui(double %a) nounwind { 53; RV64ID-LABEL: sext_fptoui: 54; RV64ID: # %bb.0: 55; RV64ID-NEXT: fmv.d.x ft0, a0 56; RV64ID-NEXT: fcvt.wu.d a0, ft0, rtz 57; RV64ID-NEXT: ret 58 %1 = fptoui double %a to i32 59 ret i32 %1 60} 61 62define zeroext i32 @zext_fptoui(double %a) nounwind { 63; RV64ID-LABEL: zext_fptoui: 64; RV64ID: # %bb.0: 65; RV64ID-NEXT: fmv.d.x ft0, a0 66; RV64ID-NEXT: fcvt.lu.d a0, ft0, rtz 67; RV64ID-NEXT: ret 68 %1 = fptoui double %a to i32 69 ret i32 %1 70} 71 72define double @uitofp_aext_i32_to_f64(i32 %a) nounwind { 73; RV64ID-LABEL: uitofp_aext_i32_to_f64: 74; RV64ID: # %bb.0: 75; RV64ID-NEXT: fcvt.d.wu ft0, a0 76; RV64ID-NEXT: fmv.x.d a0, ft0 77; RV64ID-NEXT: ret 78 %1 = uitofp i32 %a to double 79 ret double %1 80} 81 82define double @uitofp_sext_i32_to_f64(i32 signext %a) nounwind { 83; RV64ID-LABEL: uitofp_sext_i32_to_f64: 84; RV64ID: # %bb.0: 85; RV64ID-NEXT: fcvt.d.wu ft0, a0 86; RV64ID-NEXT: fmv.x.d a0, ft0 87; RV64ID-NEXT: ret 88 %1 = uitofp i32 %a to double 89 ret double %1 90} 91 92define double @uitofp_zext_i32_to_f64(i32 zeroext %a) nounwind { 93; RV64ID-LABEL: uitofp_zext_i32_to_f64: 94; RV64ID: # %bb.0: 95; RV64ID-NEXT: fcvt.d.wu ft0, a0 96; RV64ID-NEXT: fmv.x.d a0, ft0 97; RV64ID-NEXT: ret 98 %1 = uitofp i32 %a to double 99 ret double %1 100} 101 102define double @sitofp_aext_i32_to_f64(i32 %a) nounwind { 103; RV64ID-LABEL: sitofp_aext_i32_to_f64: 104; RV64ID: # %bb.0: 105; RV64ID-NEXT: fcvt.d.w ft0, a0 106; RV64ID-NEXT: fmv.x.d a0, ft0 107; RV64ID-NEXT: ret 108 %1 = sitofp i32 %a to double 109 ret double %1 110} 111 112define double @sitofp_sext_i32_to_f64(i32 signext %a) nounwind { 113; RV64ID-LABEL: sitofp_sext_i32_to_f64: 114; RV64ID: # %bb.0: 115; RV64ID-NEXT: fcvt.d.w ft0, a0 116; RV64ID-NEXT: fmv.x.d a0, ft0 117; RV64ID-NEXT: ret 118 %1 = sitofp i32 %a to double 119 ret double %1 120} 121 122define double @sitofp_zext_i32_to_f64(i32 zeroext %a) nounwind { 123; RV64ID-LABEL: sitofp_zext_i32_to_f64: 124; RV64ID: # %bb.0: 125; RV64ID-NEXT: fcvt.d.w ft0, a0 126; RV64ID-NEXT: fmv.x.d a0, ft0 127; RV64ID-NEXT: ret 128 %1 = sitofp i32 %a to double 129 ret double %1 130} 131