1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ 3; RUN: -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFH 4 5; This file exhaustively checks half<->i32 conversions. In general, 6; fcvt.l[u].h can be selected instead of fcvt.w[u].h because poison is 7; generated for an fpto[s|u]i conversion if the result doesn't fit in the 8; target type. 9 10define i32 @aext_fptosi(half %a) nounwind { 11; RV64IZFH-LABEL: aext_fptosi: 12; RV64IZFH: # %bb.0: 13; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz 14; RV64IZFH-NEXT: ret 15 %1 = fptosi half %a to i32 16 ret i32 %1 17} 18 19define signext i32 @sext_fptosi(half %a) nounwind { 20; RV64IZFH-LABEL: sext_fptosi: 21; RV64IZFH: # %bb.0: 22; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz 23; RV64IZFH-NEXT: ret 24 %1 = fptosi half %a to i32 25 ret i32 %1 26} 27 28define zeroext i32 @zext_fptosi(half %a) nounwind { 29; RV64IZFH-LABEL: zext_fptosi: 30; RV64IZFH: # %bb.0: 31; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz 32; RV64IZFH-NEXT: slli a0, a0, 32 33; RV64IZFH-NEXT: srli a0, a0, 32 34; RV64IZFH-NEXT: ret 35 %1 = fptosi half %a to i32 36 ret i32 %1 37} 38 39define i32 @aext_fptoui(half %a) nounwind { 40; RV64IZFH-LABEL: aext_fptoui: 41; RV64IZFH: # %bb.0: 42; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz 43; RV64IZFH-NEXT: ret 44 %1 = fptoui half %a to i32 45 ret i32 %1 46} 47 48define signext i32 @sext_fptoui(half %a) nounwind { 49; RV64IZFH-LABEL: sext_fptoui: 50; RV64IZFH: # %bb.0: 51; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz 52; RV64IZFH-NEXT: ret 53 %1 = fptoui half %a to i32 54 ret i32 %1 55} 56 57define zeroext i32 @zext_fptoui(half %a) nounwind { 58; RV64IZFH-LABEL: zext_fptoui: 59; RV64IZFH: # %bb.0: 60; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz 61; RV64IZFH-NEXT: ret 62 %1 = fptoui half %a to i32 63 ret i32 %1 64} 65 66define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind { 67; RV64IZFH-LABEL: bcvt_f16_to_aext_i16: 68; RV64IZFH: # %bb.0: 69; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 70; RV64IZFH-NEXT: fmv.x.h a0, ft0 71; RV64IZFH-NEXT: ret 72 %1 = fadd half %a, %b 73 %2 = bitcast half %1 to i16 74 ret i16 %2 75} 76 77define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind { 78; RV64IZFH-LABEL: bcvt_f16_to_sext_i16: 79; RV64IZFH: # %bb.0: 80; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 81; RV64IZFH-NEXT: fmv.x.h a0, ft0 82; RV64IZFH-NEXT: slli a0, a0, 48 83; RV64IZFH-NEXT: srai a0, a0, 48 84; RV64IZFH-NEXT: ret 85 %1 = fadd half %a, %b 86 %2 = bitcast half %1 to i16 87 ret i16 %2 88} 89 90define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind { 91; RV64IZFH-LABEL: bcvt_f16_to_zext_i16: 92; RV64IZFH: # %bb.0: 93; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 94; RV64IZFH-NEXT: fmv.x.h a0, ft0 95; RV64IZFH-NEXT: lui a1, 16 96; RV64IZFH-NEXT: addiw a1, a1, -1 97; RV64IZFH-NEXT: and a0, a0, a1 98; RV64IZFH-NEXT: ret 99 %1 = fadd half %a, %b 100 %2 = bitcast half %1 to i16 101 ret i16 %2 102} 103 104define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind { 105; RV64IZFH-LABEL: bcvt_i64_to_f16_via_i16: 106; RV64IZFH: # %bb.0: 107; RV64IZFH-NEXT: fmv.h.x ft0, a0 108; RV64IZFH-NEXT: fmv.h.x ft1, a1 109; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1 110; RV64IZFH-NEXT: ret 111 %1 = trunc i64 %a to i16 112 %2 = trunc i64 %b to i16 113 %3 = bitcast i16 %1 to half 114 %4 = bitcast i16 %2 to half 115 %5 = fadd half %3, %4 116 ret half %5 117} 118 119define half @uitofp_aext_i32_to_f16(i32 %a) nounwind { 120; RV64IZFH-LABEL: uitofp_aext_i32_to_f16: 121; RV64IZFH: # %bb.0: 122; RV64IZFH-NEXT: fcvt.h.wu fa0, a0 123; RV64IZFH-NEXT: ret 124 %1 = uitofp i32 %a to half 125 ret half %1 126} 127 128define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind { 129; RV64IZFH-LABEL: uitofp_sext_i32_to_f16: 130; RV64IZFH: # %bb.0: 131; RV64IZFH-NEXT: fcvt.h.wu fa0, a0 132; RV64IZFH-NEXT: ret 133 %1 = uitofp i32 %a to half 134 ret half %1 135} 136 137define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind { 138; RV64IZFH-LABEL: uitofp_zext_i32_to_f16: 139; RV64IZFH: # %bb.0: 140; RV64IZFH-NEXT: fcvt.h.wu fa0, a0 141; RV64IZFH-NEXT: ret 142 %1 = uitofp i32 %a to half 143 ret half %1 144} 145 146define half @sitofp_aext_i32_to_f16(i32 %a) nounwind { 147; RV64IZFH-LABEL: sitofp_aext_i32_to_f16: 148; RV64IZFH: # %bb.0: 149; RV64IZFH-NEXT: fcvt.h.w fa0, a0 150; RV64IZFH-NEXT: ret 151 %1 = sitofp i32 %a to half 152 ret half %1 153} 154 155define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind { 156; RV64IZFH-LABEL: sitofp_sext_i32_to_f16: 157; RV64IZFH: # %bb.0: 158; RV64IZFH-NEXT: fcvt.h.w fa0, a0 159; RV64IZFH-NEXT: ret 160 %1 = sitofp i32 %a to half 161 ret half %1 162} 163 164define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind { 165; RV64IZFH-LABEL: sitofp_zext_i32_to_f16: 166; RV64IZFH: # %bb.0: 167; RV64IZFH-NEXT: fcvt.h.w fa0, a0 168; RV64IZFH-NEXT: ret 169 %1 = sitofp i32 %a to half 170 ret half %1 171} 172