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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \
3# RUN:  | FileCheck -check-prefix=RV32I %s
4# RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \
5# RUN:  | FileCheck -check-prefix=RV64I %s
6
7# Provide dummy definitions of functions and just enough metadata to create a
8# DBG_VALUE.
9--- |
10  define void @cmov_interleaved_bad() {
11    ret void
12  }
13  define void @cmov_interleaved_debug_value() {
14    ret void
15  }
16...
17---
18# Here we have a sequence of select instructions with a non-select instruction
19# in the middle. Because the non-select depends on the result of a previous
20# select, we cannot optimize the sequence to share control-flow.
21name:            cmov_interleaved_bad
22alignment:       4
23tracksRegLiveness: true
24registers:
25  - { id: 0, class: gpr }
26  - { id: 1, class: gpr }
27  - { id: 2, class: gpr }
28  - { id: 3, class: gpr }
29  - { id: 4, class: gpr }
30  - { id: 5, class: gpr }
31  - { id: 6, class: gpr }
32  - { id: 7, class: gpr }
33  - { id: 8, class: gpr }
34  - { id: 9, class: gpr }
35  - { id: 10, class: gpr }
36liveins:
37  - { reg: '$x10', virtual-reg: '%0' }
38  - { reg: '$x11', virtual-reg: '%1' }
39  - { reg: '$x12', virtual-reg: '%2' }
40  - { reg: '$x13', virtual-reg: '%3' }
41body:             |
42  bb.0:
43    liveins: $x10, $x11, $x12, $x13
44
45    ; RV32I-LABEL: name: cmov_interleaved_bad
46    ; RV32I: successors: %bb.1, %bb.2
47    ; RV32I: liveins: $x10, $x11, $x12, $x13
48    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
49    ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
50    ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
51    ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
52    ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
53    ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
54    ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
55    ; RV32I: .1:
56    ; RV32I: .2:
57    ; RV32I: successors: %bb.3, %bb.4
58    ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
59    ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
60    ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4
61    ; RV32I: .3:
62    ; RV32I: .4:
63    ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
64    ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
65    ; RV32I: $x10 = COPY [[ADD]]
66    ; RV32I: PseudoRET implicit $x10
67    ; RV64I-LABEL: name: cmov_interleaved_bad
68    ; RV64I: successors: %bb.1, %bb.2
69    ; RV64I: liveins: $x10, $x11, $x12, $x13
70    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
71    ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
72    ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
73    ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
74    ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
75    ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
76    ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
77    ; RV64I: .1:
78    ; RV64I: .2:
79    ; RV64I: successors: %bb.3, %bb.4
80    ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
81    ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
82    ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4
83    ; RV64I: .3:
84    ; RV64I: .4:
85    ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
86    ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
87    ; RV64I: $x10 = COPY [[ADD]]
88    ; RV64I: PseudoRET implicit $x10
89    %3:gpr = COPY $x13
90    %2:gpr = COPY $x12
91    %1:gpr = COPY $x11
92    %0:gpr = COPY $x10
93    %5:gpr = ANDI %0, 1
94    %6:gpr = COPY $x0
95    %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
96    %8:gpr = ADDI %7, 1
97    %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
98    %10:gpr = ADD %7, killed %9
99    $x10 = COPY %10
100    PseudoRET implicit $x10
101
102...
103---
104# Demonstrate that debug info associated with selects is correctly moved to
105# the tail basic block, while debug info associated with non-selects is left
106# in the head basic block.
107name:            cmov_interleaved_debug_value
108alignment:       4
109tracksRegLiveness: true
110registers:
111  - { id: 0, class: gpr }
112  - { id: 1, class: gpr }
113  - { id: 2, class: gpr }
114  - { id: 3, class: gpr }
115  - { id: 4, class: gpr }
116  - { id: 5, class: gpr }
117  - { id: 6, class: gpr }
118  - { id: 7, class: gpr }
119  - { id: 8, class: gpr }
120  - { id: 9, class: gpr }
121  - { id: 10, class: gpr }
122liveins:
123  - { reg: '$x10', virtual-reg: '%0' }
124  - { reg: '$x11', virtual-reg: '%1' }
125  - { reg: '$x12', virtual-reg: '%2' }
126  - { reg: '$x13', virtual-reg: '%3' }
127body:             |
128  bb.0:
129    liveins: $x10, $x11, $x12, $x13
130
131    ; RV32I-LABEL: name: cmov_interleaved_debug_value
132    ; RV32I: successors: %bb.1, %bb.2
133    ; RV32I: liveins: $x10, $x11, $x12, $x13
134    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
135    ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
136    ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
137    ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
138    ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
139    ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
140    ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
141    ; RV32I: DBG_VALUE [[ADDI]], $noreg
142    ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
143    ; RV32I: .1:
144    ; RV32I: .2:
145    ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
146    ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
147    ; RV32I: DBG_VALUE [[PHI]], $noreg
148    ; RV32I: DBG_VALUE [[PHI1]], $noreg
149    ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
150    ; RV32I: $x10 = COPY [[ADD]]
151    ; RV32I: PseudoRET implicit $x10
152    ; RV64I-LABEL: name: cmov_interleaved_debug_value
153    ; RV64I: successors: %bb.1, %bb.2
154    ; RV64I: liveins: $x10, $x11, $x12, $x13
155    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
156    ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
157    ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
158    ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
159    ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
160    ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
161    ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
162    ; RV64I: DBG_VALUE [[ADDI]], $noreg
163    ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
164    ; RV64I: .1:
165    ; RV64I: .2:
166    ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
167    ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
168    ; RV64I: DBG_VALUE [[PHI]], $noreg
169    ; RV64I: DBG_VALUE [[PHI1]], $noreg
170    ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
171    ; RV64I: $x10 = COPY [[ADD]]
172    ; RV64I: PseudoRET implicit $x10
173    %3:gpr = COPY $x13
174    %2:gpr = COPY $x12
175    %1:gpr = COPY $x11
176    %0:gpr = COPY $x10
177    %5:gpr = ANDI %0, 1
178    %6:gpr = COPY $x0
179    %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
180    DBG_VALUE %7, $noreg
181    %8:gpr = ADDI %0, 1
182    DBG_VALUE %8, $noreg
183    %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
184    DBG_VALUE %9, $noreg
185    %10:gpr = ADD %7, killed %9
186    $x10 = COPY %10
187    PseudoRET implicit $x10
188
189...
190---
191