1# Test 64-bit COMPARE LOGICAL AND BRANCH in cases where the sheer number of 2# instructions causes some branches to be out of range. 3# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s 4 5# Construct: 6# 7# before0: 8# conditional branch to after0 9# ... 10# beforeN: 11# conditional branch to after0 12# main: 13# 0xffcc bytes, from MVIY instructions 14# conditional branch to main 15# after0: 16# ... 17# conditional branch to main 18# afterN: 19# 20# Each conditional branch sequence occupies 12 bytes if it uses a short 21# branch and 16 if it uses a long one. The ones before "main:" have to 22# take the branch length into account, which is 6 for short branches, 23# so the final (0x34 - 6) / 12 == 3 blocks can use short branches. 24# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks 25# can use short branches. The conservative algorithm we use makes 26# one of the forward branches unnecessarily long, as noted in the 27# check output below. 28# 29# CHECK: lgb [[REG:%r[0-5]]], 0(%r3) 30# CHECK: clgr %r4, [[REG]] 31# CHECK: jgl [[LABEL:\.L[^ ]*]] 32# CHECK: lgb [[REG:%r[0-5]]], 1(%r3) 33# CHECK: clgr %r4, [[REG]] 34# CHECK: jgl [[LABEL]] 35# CHECK: lgb [[REG:%r[0-5]]], 2(%r3) 36# CHECK: clgr %r4, [[REG]] 37# CHECK: jgl [[LABEL]] 38# CHECK: lgb [[REG:%r[0-5]]], 3(%r3) 39# CHECK: clgr %r4, [[REG]] 40# CHECK: jgl [[LABEL]] 41# CHECK: lgb [[REG:%r[0-5]]], 4(%r3) 42# CHECK: clgr %r4, [[REG]] 43# CHECK: jgl [[LABEL]] 44# ...as mentioned above, the next one could be a CLGRJL instead... 45# CHECK: lgb [[REG:%r[0-5]]], 5(%r3) 46# CHECK: clgr %r4, [[REG]] 47# CHECK: jgl [[LABEL]] 48# CHECK: lgb [[REG:%r[0-5]]], 6(%r3) 49# CHECK: clgrjl %r4, [[REG]], [[LABEL]] 50# CHECK: lgb [[REG:%r[0-5]]], 7(%r3) 51# CHECK: clgrjl %r4, [[REG]], [[LABEL]] 52# ...main goes here... 53# CHECK: lgb [[REG:%r[0-5]]], 25(%r3) 54# CHECK: clgrjl %r4, [[REG]], [[LABEL:\.L[^ ]*]] 55# CHECK: lgb [[REG:%r[0-5]]], 26(%r3) 56# CHECK: clgrjl %r4, [[REG]], [[LABEL]] 57# CHECK: lgb [[REG:%r[0-5]]], 27(%r3) 58# CHECK: clgrjl %r4, [[REG]], [[LABEL]] 59# CHECK: lgb [[REG:%r[0-5]]], 28(%r3) 60# CHECK: clgrjl %r4, [[REG]], [[LABEL]] 61# CHECK: lgb [[REG:%r[0-5]]], 29(%r3) 62# CHECK: clgr %r4, [[REG]] 63# CHECK: jgl [[LABEL]] 64# CHECK: lgb [[REG:%r[0-5]]], 30(%r3) 65# CHECK: clgr %r4, [[REG]] 66# CHECK: jgl [[LABEL]] 67# CHECK: lgb [[REG:%r[0-5]]], 31(%r3) 68# CHECK: clgr %r4, [[REG]] 69# CHECK: jgl [[LABEL]] 70# CHECK: lgb [[REG:%r[0-5]]], 32(%r3) 71# CHECK: clgr %r4, [[REG]] 72# CHECK: jgl [[LABEL]] 73 74from __future__ import print_function 75 76branch_blocks = 8 77main_size = 0xffcc 78 79print('@global = global i32 0') 80 81print('define void @f1(i8 *%base, i8 *%stop, i64 %limit) {') 82print('entry:') 83print(' br label %before0') 84print('') 85 86for i in range(branch_blocks): 87 next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' 88 print('before%d:' % i) 89 print(' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i)) 90 print(' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i)) 91 print(' %%bext%d = sext i8 %%bcur%d to i64' % (i, i)) 92 print(' %%btest%d = icmp ult i64 %%limit, %%bext%d' % (i, i)) 93 print(' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)) 94 print('') 95 96print('%s:' % next) 97a, b = 1, 1 98for i in range(0, main_size, 6): 99 a, b = b, a + b 100 offset = 4096 + b % 500000 101 value = a % 256 102 print(' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)) 103 print(' store volatile i8 %d, i8 *%%ptr%d' % (value, i)) 104 105for i in range(branch_blocks): 106 print(' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25)) 107 print(' %%acur%d = load i8 , i8 *%%astop%d' % (i, i)) 108 print(' %%aext%d = sext i8 %%acur%d to i64' % (i, i)) 109 print(' %%atest%d = icmp ult i64 %%limit, %%aext%d' % (i, i)) 110 print(' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)) 111 print('') 112 print('after%d:' % i) 113 114print(' %dummy = load volatile i32, i32 *@global') 115print(' ret void') 116print('}') 117