1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; Test sequences that can use RISBG with a normal first operand. 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 5 6; Test a case with two ANDs. 7define i32 @f1(i32 %a, i32 %b) { 8; CHECK-LABEL: f1: 9; CHECK: # %bb.0: 10; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d 11; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 12; CHECK-NEXT: risbg %r2, %r3, 60, 62, 0 13; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 14; CHECK-NEXT: br %r14 15 %anda = and i32 %a, -15 16 %andb = and i32 %b, 14 17 %or = or i32 %anda, %andb 18 ret i32 %or 19} 20 21; ...and again with i64. 22define i64 @f2(i64 %a, i64 %b) { 23; CHECK-LABEL: f2: 24; CHECK: # %bb.0: 25; CHECK-NEXT: risbg %r2, %r3, 60, 62, 0 26; CHECK-NEXT: br %r14 27 %anda = and i64 %a, -15 28 %andb = and i64 %b, 14 29 %or = or i64 %anda, %andb 30 ret i64 %or 31} 32 33; Test a case with two ANDs and a shift. 34define i32 @f3(i32 %a, i32 %b) { 35; CHECK-LABEL: f3: 36; CHECK: # %bb.0: 37; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d 38; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 39; CHECK-NEXT: risbg %r2, %r3, 60, 63, 56 40; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 41; CHECK-NEXT: br %r14 42 %anda = and i32 %a, -16 43 %shr = lshr i32 %b, 8 44 %andb = and i32 %shr, 15 45 %or = or i32 %anda, %andb 46 ret i32 %or 47} 48 49; ...and again with i64. 50define i64 @f4(i64 %a, i64 %b) { 51; CHECK-LABEL: f4: 52; CHECK: # %bb.0: 53; CHECK-NEXT: risbg %r2, %r3, 60, 63, 56 54; CHECK-NEXT: br %r14 55 %anda = and i64 %a, -16 56 %shr = lshr i64 %b, 8 57 %andb = and i64 %shr, 15 58 %or = or i64 %anda, %andb 59 ret i64 %or 60} 61 62; Test a case with a single AND and a left shift. 63define i32 @f5(i32 %a, i32 %b) { 64; CHECK-LABEL: f5: 65; CHECK: # %bb.0: 66; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d 67; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 68; CHECK-NEXT: risbg %r2, %r3, 32, 53, 10 69; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 70; CHECK-NEXT: br %r14 71 %anda = and i32 %a, 1023 72 %shlb = shl i32 %b, 10 73 %or = or i32 %anda, %shlb 74 ret i32 %or 75} 76 77; ...and again with i64. 78define i64 @f6(i64 %a, i64 %b) { 79; CHECK-LABEL: f6: 80; CHECK: # %bb.0: 81; CHECK-NEXT: risbg %r2, %r3, 0, 53, 10 82; CHECK-NEXT: br %r14 83 %anda = and i64 %a, 1023 84 %shlb = shl i64 %b, 10 85 %or = or i64 %anda, %shlb 86 ret i64 %or 87} 88 89; Test a case with a single AND and a right shift. 90define i32 @f7(i32 %a, i32 %b) { 91; CHECK-LABEL: f7: 92; CHECK: # %bb.0: 93; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d 94; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 95; CHECK-NEXT: risbg %r2, %r3, 40, 63, 56 96; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 97; CHECK-NEXT: br %r14 98 %anda = and i32 %a, -16777216 99 %shrb = lshr i32 %b, 8 100 %or = or i32 %anda, %shrb 101 ret i32 %or 102} 103 104; ...and again with i64. 105define i64 @f8(i64 %a, i64 %b) { 106; CHECK-LABEL: f8: 107; CHECK: # %bb.0: 108; CHECK-NEXT: risbg %r2, %r3, 8, 63, 56 109; CHECK-NEXT: br %r14 110 %anda = and i64 %a, -72057594037927936 111 %shrb = lshr i64 %b, 8 112 %or = or i64 %anda, %shrb 113 ret i64 %or 114} 115 116; Check that we can get the case where a 64-bit shift feeds a 32-bit or of 117; ands with complement masks. 118define signext i32 @f9(i64 %x, i32 signext %y) { 119; CHECK-LABEL: f9: 120; CHECK: # %bb.0: 121; CHECK-NEXT: risbg %r3, %r2, 48, 63, 16 122; CHECK-NEXT: lgfr %r2, %r3 123; CHECK-NEXT: br %r14 124 %shr6 = lshr i64 %x, 48 125 %conv = trunc i64 %shr6 to i32 126 %and1 = and i32 %y, -65536 127 %or = or i32 %conv, %and1 128 ret i32 %or 129} 130 131; Check that we don't get the case where a 64-bit shift feeds a 32-bit or of 132; ands with incompatible masks. 133define signext i32 @f10(i64 %x, i32 signext %y) { 134; CHECK-LABEL: f10: 135; CHECK: # %bb.0: 136; CHECK-NEXT: nilf %r3, 4278190080 137; CHECK-NEXT: rosbg %r3, %r2, 48, 63, 16 138; CHECK-NEXT: lgfr %r2, %r3 139; CHECK-NEXT: br %r14 140 %shr6 = lshr i64 %x, 48 141 %conv = trunc i64 %shr6 to i32 142 %and1 = and i32 %y, -16777216 143 %or = or i32 %conv, %and1 144 ret i32 %or 145} 146