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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test that the case of (64 - shift) used by a shift/rotate instruction is
3; implemented with an lcr. This should also work for any multiple of 64.
4;
5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
6
7define i64 @f1(i64 %in, i64 %sh) {
8; CHECK-LABEL: f1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    lcr %r1, %r3
11; CHECK-NEXT:    sllg %r2, %r2, 0(%r1)
12; CHECK-NEXT:    br %r14
13  %sub = sub i64 64, %sh
14  %shl = shl i64 %in, %sub
15  ret i64 %shl
16}
17
18define i64 @f2(i64 %in, i64 %sh) {
19; CHECK-LABEL: f2:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    lcr %r1, %r3
22; CHECK-NEXT:    srag %r2, %r2, 0(%r1)
23; CHECK-NEXT:    br %r14
24  %sub = sub i64 64, %sh
25  %shl = ashr i64 %in, %sub
26  ret i64 %shl
27}
28
29define i64 @f3(i64 %in, i64 %sh) {
30; CHECK-LABEL: f3:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    lcr %r1, %r3
33; CHECK-NEXT:    srlg %r2, %r2, 0(%r1)
34; CHECK-NEXT:    br %r14
35  %sub = sub i64 64, %sh
36  %shl = lshr i64 %in, %sub
37  ret i64 %shl
38}
39
40define i64 @f4(i64 %in, i64 %sh) {
41; CHECK-LABEL: f4:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    lcr %r1, %r3
44; CHECK-NEXT:    rllg %r2, %r2, 0(%r1)
45; CHECK-NEXT:    br %r14
46  %shr = lshr i64 %in, %sh
47  %sub = sub i64 64, %sh
48  %shl = shl i64 %in, %sub
49  %or = or i64 %shl, %shr
50  ret i64 %or
51}
52
53define i64 @f5(i64 %in, i64 %sh) {
54; CHECK-LABEL: f5:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    lcr %r1, %r3
57; CHECK-NEXT:    sllg %r2, %r2, 0(%r1)
58; CHECK-NEXT:    br %r14
59  %sub = sub i64 128, %sh
60  %shl = shl i64 %in, %sub
61  ret i64 %shl
62}
63
64define i64 @f6(i64 %in, i64 %sh) {
65; CHECK-LABEL: f6:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    lcr %r1, %r3
68; CHECK-NEXT:    srag %r2, %r2, 0(%r1)
69; CHECK-NEXT:    br %r14
70  %sub = sub i64 256, %sh
71  %shl = ashr i64 %in, %sub
72  ret i64 %shl
73}
74
75define i64 @f7(i64 %in, i64 %sh) {
76; CHECK-LABEL: f7:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    lcr %r1, %r3
79; CHECK-NEXT:    srlg %r2, %r2, 0(%r1)
80; CHECK-NEXT:    br %r14
81  %sub = sub i64 512, %sh
82  %shl = lshr i64 %in, %sub
83  ret i64 %shl
84}
85
86define i64 @f8(i64 %in, i64 %sh) {
87; CHECK-LABEL: f8:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    lcr %r1, %r3
90; CHECK-NEXT:    srlg %r0, %r2, 0(%r3)
91; CHECK-NEXT:    sllg %r2, %r2, 0(%r1)
92; CHECK-NEXT:    ogr %r2, %r0
93; CHECK-NEXT:    br %r14
94  %shr = lshr i64 %in, %sh
95  %sub = sub i64 1024, %sh
96  %shl = shl i64 %in, %sub
97  %or = or i64 %shl, %shr
98  ret i64 %or
99}
100