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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test compound shifts.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5
6; Test a shift right followed by a sign extension.  This can use two shifts.
7define i64 @f1(i32 %a) {
8; CHECK-LABEL: f1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
11; CHECK-NEXT:    risbg %r0, %r2, 63, 191, 63
12; CHECK-NEXT:    lcgr %r2, %r0
13; CHECK-NEXT:    br %r14
14  %shr = lshr i32 %a, 1
15  %trunc = trunc i32 %shr to i1
16  %ext = sext i1 %trunc to i64
17  ret i64 %ext
18}
19
20; ...and again with the highest shift count that doesn't reduce to an
21; ashr/sext pair.
22define i64 @f2(i32 %a) {
23; CHECK-LABEL: f2:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
26; CHECK-NEXT:    risbg %r0, %r2, 63, 191, 34
27; CHECK-NEXT:    lcgr %r2, %r0
28; CHECK-NEXT:    br %r14
29  %shr = lshr i32 %a, 30
30  %trunc = trunc i32 %shr to i1
31  %ext = sext i1 %trunc to i64
32  ret i64 %ext
33}
34
35; Test a left shift that of an extended right shift in a case where folding
36; is possible.
37define i64 @f3(i32 %a) {
38; CHECK-LABEL: f3:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
41; CHECK-NEXT:    risbg %r2, %r2, 27, 181, 9
42; CHECK-NEXT:    br %r14
43  %shr = lshr i32 %a, 1
44  %ext = zext i32 %shr to i64
45  %shl = shl i64 %ext, 10
46  %and = and i64 %shl, 137438952960
47  ret i64 %and
48}
49
50; ...and again with a larger right shift.
51define i64 @f4(i32 %a) {
52; CHECK-LABEL: f4:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
55; CHECK-NEXT:    risbg %r2, %r2, 30, 158, 3
56; CHECK-NEXT:    br %r14
57  %shr = lshr i32 %a, 30
58  %ext = sext i32 %shr to i64
59  %shl = shl i64 %ext, 33
60  %and = and i64 %shl, 8589934592
61  ret i64 %and
62}
63
64; Repeat the previous test in a case where all bits outside the
65; bottom 3 matter.
66define i64 @f5(i32 %a) {
67; CHECK-LABEL: f5:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
70; CHECK-NEXT:    risbg %r2, %r2, 29, 158, 3
71; CHECK-NEXT:    lhi %r2, 7
72; CHECK-NEXT:    br %r14
73  %shr = lshr i32 %a, 30
74  %ext = sext i32 %shr to i64
75  %shl = shl i64 %ext, 33
76  %or = or i64 %shl, 7
77  ret i64 %or
78}
79
80; Test that SRA gets replaced with SRL if the sign bit is the only one
81; that matters.
82define i64 @f6(i64 %a) {
83; CHECK-LABEL: f6:
84; CHECK:       # %bb.0:
85; CHECK-NEXT:    risbg %r2, %r2, 55, 183, 19
86; CHECK-NEXT:    br %r14
87  %shl = shl i64 %a, 10
88  %shr = ashr i64 %shl, 60
89  %and = and i64 %shr, 256
90  ret i64 %and
91}
92
93; Test another form of f1.
94define i64 @f7(i32 %a) {
95; CHECK-LABEL: f7:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
98; CHECK-NEXT:    sllg %r0, %r2, 62
99; CHECK-NEXT:    srag %r2, %r0, 63
100; CHECK-NEXT:    br %r14
101  %1 = shl i32 %a, 30
102  %sext = ashr i32 %1, 31
103  %ext = sext i32 %sext to i64
104  ret i64 %ext
105}
106