1; Test vector zero extensions, which need to be implemented as ANDs. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5; Test a v16i1->v16i8 extension. 6define <16 x i8> @f1(<16 x i8> %val) { 7; CHECK-LABEL: f1: 8; CHECK: vrepib [[REG:%v[0-9]+]], 1 9; CHECK: vn %v24, %v24, [[REG]] 10; CHECK: br %r14 11 %trunc = trunc <16 x i8> %val to <16 x i1> 12 %ret = zext <16 x i1> %trunc to <16 x i8> 13 ret <16 x i8> %ret 14} 15 16; Test a v8i1->v8i16 extension. 17define <8 x i16> @f2(<8 x i16> %val) { 18; CHECK-LABEL: f2: 19; CHECK: vrepih [[REG:%v[0-9]+]], 1 20; CHECK: vn %v24, %v24, [[REG]] 21; CHECK: br %r14 22 %trunc = trunc <8 x i16> %val to <8 x i1> 23 %ret = zext <8 x i1> %trunc to <8 x i16> 24 ret <8 x i16> %ret 25} 26 27; Test a v8i8->v8i16 extension. 28define <8 x i16> @f3(<8 x i16> %val) { 29; CHECK-LABEL: f3: 30; CHECK: vgbm [[REG:%v[0-9]+]], 21845 31; CHECK: vn %v24, %v24, [[REG]] 32; CHECK: br %r14 33 %trunc = trunc <8 x i16> %val to <8 x i8> 34 %ret = zext <8 x i8> %trunc to <8 x i16> 35 ret <8 x i16> %ret 36} 37 38; Test a v4i1->v4i32 extension. 39define <4 x i32> @f4(<4 x i32> %val) { 40; CHECK-LABEL: f4: 41; CHECK: vrepif [[REG:%v[0-9]+]], 1 42; CHECK: vn %v24, %v24, [[REG]] 43; CHECK: br %r14 44 %trunc = trunc <4 x i32> %val to <4 x i1> 45 %ret = zext <4 x i1> %trunc to <4 x i32> 46 ret <4 x i32> %ret 47} 48 49; Test a v4i8->v4i32 extension. 50define <4 x i32> @f5(<4 x i32> %val) { 51; CHECK-LABEL: f5: 52; CHECK: vgbm [[REG:%v[0-9]+]], 4369 53; CHECK: vn %v24, %v24, [[REG]] 54; CHECK: br %r14 55 %trunc = trunc <4 x i32> %val to <4 x i8> 56 %ret = zext <4 x i8> %trunc to <4 x i32> 57 ret <4 x i32> %ret 58} 59 60; Test a v4i16->v4i32 extension. 61define <4 x i32> @f6(<4 x i32> %val) { 62; CHECK-LABEL: f6: 63; CHECK: vgbm [[REG:%v[0-9]+]], 13107 64; CHECK: vn %v24, %v24, [[REG]] 65; CHECK: br %r14 66 %trunc = trunc <4 x i32> %val to <4 x i16> 67 %ret = zext <4 x i16> %trunc to <4 x i32> 68 ret <4 x i32> %ret 69} 70 71; Test a v2i1->v2i64 extension. 72define <2 x i64> @f7(<2 x i64> %val) { 73; CHECK-LABEL: f7: 74; CHECK: vrepig [[REG:%v[0-9]+]], 1 75; CHECK: vn %v24, %v24, [[REG]] 76; CHECK: br %r14 77 %trunc = trunc <2 x i64> %val to <2 x i1> 78 %ret = zext <2 x i1> %trunc to <2 x i64> 79 ret <2 x i64> %ret 80} 81 82; Test a v2i8->v2i64 extension. 83define <2 x i64> @f8(<2 x i64> %val) { 84; CHECK-LABEL: f8: 85; CHECK: vgbm [[REG:%v[0-9]+]], 257 86; CHECK: vn %v24, %v24, [[REG]] 87; CHECK: br %r14 88 %trunc = trunc <2 x i64> %val to <2 x i8> 89 %ret = zext <2 x i8> %trunc to <2 x i64> 90 ret <2 x i64> %ret 91} 92 93; Test a v2i16->v2i64 extension. 94define <2 x i64> @f9(<2 x i64> %val) { 95; CHECK-LABEL: f9: 96; CHECK: vgbm [[REG:%v[0-9]+]], 771 97; CHECK: vn %v24, %v24, [[REG]] 98; CHECK: br %r14 99 %trunc = trunc <2 x i64> %val to <2 x i16> 100 %ret = zext <2 x i16> %trunc to <2 x i64> 101 ret <2 x i64> %ret 102} 103 104; Test a v2i32->v2i64 extension. 105define <2 x i64> @f10(<2 x i64> %val) { 106; CHECK-LABEL: f10: 107; CHECK: vgbm [[REG:%v[0-9]+]], 3855 108; CHECK: vn %v24, %v24, [[REG]] 109; CHECK: br %r14 110 %trunc = trunc <2 x i64> %val to <2 x i32> 111 %ret = zext <2 x i32> %trunc to <2 x i64> 112 ret <2 x i64> %ret 113} 114