1; Test f32 and v4f32 comparisons on z14. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s 4 5; Test oeq. 6define <4 x i32> @f1(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 7; CHECK-LABEL: f1: 8; CHECK: vfcesb %v24, %v26, %v28 9; CHECK-NEXT: br %r14 10 %cmp = fcmp oeq <4 x float> %val1, %val2 11 %ret = sext <4 x i1> %cmp to <4 x i32> 12 ret <4 x i32> %ret 13} 14 15; Test one. 16define <4 x i32> @f2(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 17; CHECK-LABEL: f2: 18; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26 19; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v26, %v28 20; CHECK: vo %v24, [[REG1]], [[REG2]] 21; CHECK-NEXT: br %r14 22 %cmp = fcmp one <4 x float> %val1, %val2 23 %ret = sext <4 x i1> %cmp to <4 x i32> 24 ret <4 x i32> %ret 25} 26 27; Test ogt. 28define <4 x i32> @f3(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 29; CHECK-LABEL: f3: 30; CHECK: vfchsb %v24, %v26, %v28 31; CHECK-NEXT: br %r14 32 %cmp = fcmp ogt <4 x float> %val1, %val2 33 %ret = sext <4 x i1> %cmp to <4 x i32> 34 ret <4 x i32> %ret 35} 36 37; Test oge. 38define <4 x i32> @f4(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 39; CHECK-LABEL: f4: 40; CHECK: vfchesb %v24, %v26, %v28 41; CHECK-NEXT: br %r14 42 %cmp = fcmp oge <4 x float> %val1, %val2 43 %ret = sext <4 x i1> %cmp to <4 x i32> 44 ret <4 x i32> %ret 45} 46 47; Test ole. 48define <4 x i32> @f5(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 49; CHECK-LABEL: f5: 50; CHECK: vfchesb %v24, %v28, %v26 51; CHECK-NEXT: br %r14 52 %cmp = fcmp ole <4 x float> %val1, %val2 53 %ret = sext <4 x i1> %cmp to <4 x i32> 54 ret <4 x i32> %ret 55} 56 57; Test olt. 58define <4 x i32> @f6(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 59; CHECK-LABEL: f6: 60; CHECK: vfchsb %v24, %v28, %v26 61; CHECK-NEXT: br %r14 62 %cmp = fcmp olt <4 x float> %val1, %val2 63 %ret = sext <4 x i1> %cmp to <4 x i32> 64 ret <4 x i32> %ret 65} 66 67; Test ueq. 68define <4 x i32> @f7(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 69; CHECK-LABEL: f7: 70; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26 71; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v26, %v28 72; CHECK: vno %v24, [[REG1]], [[REG2]] 73; CHECK-NEXT: br %r14 74 %cmp = fcmp ueq <4 x float> %val1, %val2 75 %ret = sext <4 x i1> %cmp to <4 x i32> 76 ret <4 x i32> %ret 77} 78 79; Test une. 80define <4 x i32> @f8(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 81; CHECK-LABEL: f8: 82; CHECK: vfcesb [[REG:%v[0-9]+]], %v26, %v28 83; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 84; CHECK-NEXT: br %r14 85 %cmp = fcmp une <4 x float> %val1, %val2 86 %ret = sext <4 x i1> %cmp to <4 x i32> 87 ret <4 x i32> %ret 88} 89 90; Test ugt. 91define <4 x i32> @f9(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) { 92; CHECK-LABEL: f9: 93; CHECK: vfchesb [[REG:%v[0-9]+]], %v28, %v26 94; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 95; CHECK-NEXT: br %r14 96 %cmp = fcmp ugt <4 x float> %val1, %val2 97 %ret = sext <4 x i1> %cmp to <4 x i32> 98 ret <4 x i32> %ret 99} 100 101; Test uge. 102define <4 x i32> @f10(<4 x i32> %dummy, <4 x float> %val1, 103 <4 x float> %val2) { 104; CHECK-LABEL: f10: 105; CHECK: vfchsb [[REG:%v[0-9]+]], %v28, %v26 106; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 107; CHECK-NEXT: br %r14 108 %cmp = fcmp uge <4 x float> %val1, %val2 109 %ret = sext <4 x i1> %cmp to <4 x i32> 110 ret <4 x i32> %ret 111} 112 113; Test ule. 114define <4 x i32> @f11(<4 x i32> %dummy, <4 x float> %val1, 115 <4 x float> %val2) { 116; CHECK-LABEL: f11: 117; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v28 118; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 119; CHECK-NEXT: br %r14 120 %cmp = fcmp ule <4 x float> %val1, %val2 121 %ret = sext <4 x i1> %cmp to <4 x i32> 122 ret <4 x i32> %ret 123} 124 125; Test ult. 126define <4 x i32> @f12(<4 x i32> %dummy, <4 x float> %val1, 127 <4 x float> %val2) { 128; CHECK-LABEL: f12: 129; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v28 130; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 131; CHECK-NEXT: br %r14 132 %cmp = fcmp ult <4 x float> %val1, %val2 133 %ret = sext <4 x i1> %cmp to <4 x i32> 134 ret <4 x i32> %ret 135} 136 137; Test ord. 138define <4 x i32> @f13(<4 x i32> %dummy, <4 x float> %val1, 139 <4 x float> %val2) { 140; CHECK-LABEL: f13: 141; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26 142; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v26, %v28 143; CHECK: vo %v24, [[REG1]], [[REG2]] 144; CHECK-NEXT: br %r14 145 %cmp = fcmp ord <4 x float> %val1, %val2 146 %ret = sext <4 x i1> %cmp to <4 x i32> 147 ret <4 x i32> %ret 148} 149 150; Test uno. 151define <4 x i32> @f14(<4 x i32> %dummy, <4 x float> %val1, 152 <4 x float> %val2) { 153; CHECK-LABEL: f14: 154; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26 155; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v26, %v28 156; CHECK: vno %v24, [[REG1]], [[REG2]] 157; CHECK-NEXT: br %r14 158 %cmp = fcmp uno <4 x float> %val1, %val2 159 %ret = sext <4 x i1> %cmp to <4 x i32> 160 ret <4 x i32> %ret 161} 162 163; Test oeq selects. 164define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2, 165 <4 x float> %val3, <4 x float> %val4) { 166; CHECK-LABEL: f15: 167; CHECK: vfcesb [[REG:%v[0-9]+]], %v24, %v26 168; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 169; CHECK-NEXT: br %r14 170 %cmp = fcmp oeq <4 x float> %val1, %val2 171 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 172 ret <4 x float> %ret 173} 174 175; Test one selects. 176define <4 x float> @f16(<4 x float> %val1, <4 x float> %val2, 177 <4 x float> %val3, <4 x float> %val4) { 178; CHECK-LABEL: f16: 179; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24 180; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v24, %v26 181; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] 182; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 183; CHECK-NEXT: br %r14 184 %cmp = fcmp one <4 x float> %val1, %val2 185 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 186 ret <4 x float> %ret 187} 188 189; Test ogt selects. 190define <4 x float> @f17(<4 x float> %val1, <4 x float> %val2, 191 <4 x float> %val3, <4 x float> %val4) { 192; CHECK-LABEL: f17: 193; CHECK: vfchsb [[REG:%v[0-9]+]], %v24, %v26 194; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 195; CHECK-NEXT: br %r14 196 %cmp = fcmp ogt <4 x float> %val1, %val2 197 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 198 ret <4 x float> %ret 199} 200 201; Test oge selects. 202define <4 x float> @f18(<4 x float> %val1, <4 x float> %val2, 203 <4 x float> %val3, <4 x float> %val4) { 204; CHECK-LABEL: f18: 205; CHECK: vfchesb [[REG:%v[0-9]+]], %v24, %v26 206; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 207; CHECK-NEXT: br %r14 208 %cmp = fcmp oge <4 x float> %val1, %val2 209 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 210 ret <4 x float> %ret 211} 212 213; Test ole selects. 214define <4 x float> @f19(<4 x float> %val1, <4 x float> %val2, 215 <4 x float> %val3, <4 x float> %val4) { 216; CHECK-LABEL: f19: 217; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v24 218; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 219; CHECK-NEXT: br %r14 220 %cmp = fcmp ole <4 x float> %val1, %val2 221 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 222 ret <4 x float> %ret 223} 224 225; Test olt selects. 226define <4 x float> @f20(<4 x float> %val1, <4 x float> %val2, 227 <4 x float> %val3, <4 x float> %val4) { 228; CHECK-LABEL: f20: 229; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v24 230; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 231; CHECK-NEXT: br %r14 232 %cmp = fcmp olt <4 x float> %val1, %val2 233 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 234 ret <4 x float> %ret 235} 236 237; Test ueq selects. 238define <4 x float> @f21(<4 x float> %val1, <4 x float> %val2, 239 <4 x float> %val3, <4 x float> %val4) { 240; CHECK-LABEL: f21: 241; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24 242; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v24, %v26 243; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] 244; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 245; CHECK-NEXT: br %r14 246 %cmp = fcmp ueq <4 x float> %val1, %val2 247 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 248 ret <4 x float> %ret 249} 250 251; Test une selects. 252define <4 x float> @f22(<4 x float> %val1, <4 x float> %val2, 253 <4 x float> %val3, <4 x float> %val4) { 254; CHECK-LABEL: f22: 255; CHECK: vfcesb [[REG:%v[0-9]+]], %v24, %v26 256; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 257; CHECK-NEXT: br %r14 258 %cmp = fcmp une <4 x float> %val1, %val2 259 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 260 ret <4 x float> %ret 261} 262 263; Test ugt selects. 264define <4 x float> @f23(<4 x float> %val1, <4 x float> %val2, 265 <4 x float> %val3, <4 x float> %val4) { 266; CHECK-LABEL: f23: 267; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v24 268; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 269; CHECK-NEXT: br %r14 270 %cmp = fcmp ugt <4 x float> %val1, %val2 271 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 272 ret <4 x float> %ret 273} 274 275; Test uge selects. 276define <4 x float> @f24(<4 x float> %val1, <4 x float> %val2, 277 <4 x float> %val3, <4 x float> %val4) { 278; CHECK-LABEL: f24: 279; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v24 280; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 281; CHECK-NEXT: br %r14 282 %cmp = fcmp uge <4 x float> %val1, %val2 283 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 284 ret <4 x float> %ret 285} 286 287; Test ule selects. 288define <4 x float> @f25(<4 x float> %val1, <4 x float> %val2, 289 <4 x float> %val3, <4 x float> %val4) { 290; CHECK-LABEL: f25: 291; CHECK: vfchsb [[REG:%v[0-9]+]], %v24, %v26 292; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 293; CHECK-NEXT: br %r14 294 %cmp = fcmp ule <4 x float> %val1, %val2 295 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 296 ret <4 x float> %ret 297} 298 299; Test ult selects. 300define <4 x float> @f26(<4 x float> %val1, <4 x float> %val2, 301 <4 x float> %val3, <4 x float> %val4) { 302; CHECK-LABEL: f26: 303; CHECK: vfchesb [[REG:%v[0-9]+]], %v24, %v26 304; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 305; CHECK-NEXT: br %r14 306 %cmp = fcmp ult <4 x float> %val1, %val2 307 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 308 ret <4 x float> %ret 309} 310 311; Test ord selects. 312define <4 x float> @f27(<4 x float> %val1, <4 x float> %val2, 313 <4 x float> %val3, <4 x float> %val4) { 314; CHECK-LABEL: f27: 315; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24 316; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v24, %v26 317; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] 318; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 319; CHECK-NEXT: br %r14 320 %cmp = fcmp ord <4 x float> %val1, %val2 321 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 322 ret <4 x float> %ret 323} 324 325; Test uno selects. 326define <4 x float> @f28(<4 x float> %val1, <4 x float> %val2, 327 <4 x float> %val3, <4 x float> %val4) { 328; CHECK-LABEL: f28: 329; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24 330; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v24, %v26 331; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] 332; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 333; CHECK-NEXT: br %r14 334 %cmp = fcmp uno <4 x float> %val1, %val2 335 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 336 ret <4 x float> %ret 337} 338 339; Test an f32 comparison that uses vector registers. 340define i64 @f29(i64 %a, i64 %b, float %f1, <4 x float> %vec) { 341; CHECK-LABEL: f29: 342; CHECK: wfcsb %f0, %v24 343; CHECK-NEXT: locgrne %r2, %r3 344; CHECK: br %r14 345 %f2 = extractelement <4 x float> %vec, i32 0 346 %cond = fcmp oeq float %f1, %f2 347 %res = select i1 %cond, i64 %a, i64 %b 348 ret i64 %res 349} 350