1; Test vector stores. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5; Test v16i8 stores. 6define void @f1(<16 x i8> %val, <16 x i8> *%ptr) { 7; CHECK-LABEL: f1: 8; CHECK: vst %v24, 0(%r2), 3 9; CHECK: br %r14 10 store <16 x i8> %val, <16 x i8> *%ptr 11 ret void 12} 13 14; Test v8i16 stores. 15define void @f2(<8 x i16> %val, <8 x i16> *%ptr) { 16; CHECK-LABEL: f2: 17; CHECK: vst %v24, 0(%r2), 3 18; CHECK: br %r14 19 store <8 x i16> %val, <8 x i16> *%ptr 20 ret void 21} 22 23; Test v4i32 stores. 24define void @f3(<4 x i32> %val, <4 x i32> *%ptr) { 25; CHECK-LABEL: f3: 26; CHECK: vst %v24, 0(%r2), 3 27; CHECK: br %r14 28 store <4 x i32> %val, <4 x i32> *%ptr 29 ret void 30} 31 32; Test v2i64 stores. 33define void @f4(<2 x i64> %val, <2 x i64> *%ptr) { 34; CHECK-LABEL: f4: 35; CHECK: vst %v24, 0(%r2), 3 36; CHECK: br %r14 37 store <2 x i64> %val, <2 x i64> *%ptr 38 ret void 39} 40 41; Test v4f32 stores. 42define void @f5(<4 x float> %val, <4 x float> *%ptr) { 43; CHECK-LABEL: f5: 44; CHECK: vst %v24, 0(%r2), 3 45; CHECK: br %r14 46 store <4 x float> %val, <4 x float> *%ptr 47 ret void 48} 49 50; Test v2f64 stores. 51define void @f6(<2 x double> %val, <2 x double> *%ptr) { 52; CHECK-LABEL: f6: 53; CHECK: vst %v24, 0(%r2), 3 54; CHECK: br %r14 55 store <2 x double> %val, <2 x double> *%ptr 56 ret void 57} 58 59; Test the highest aligned in-range offset. 60define void @f7(<16 x i8> %val, <16 x i8> *%base) { 61; CHECK-LABEL: f7: 62; CHECK: vst %v24, 4080(%r2), 3 63; CHECK: br %r14 64 %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255 65 store <16 x i8> %val, <16 x i8> *%ptr 66 ret void 67} 68 69; Test the highest unaligned in-range offset. 70define void @f8(<16 x i8> %val, i8 *%base) { 71; CHECK-LABEL: f8: 72; CHECK: vst %v24, 4095(%r2) 73; CHECK: br %r14 74 %addr = getelementptr i8, i8 *%base, i64 4095 75 %ptr = bitcast i8 *%addr to <16 x i8> * 76 store <16 x i8> %val, <16 x i8> *%ptr, align 1 77 ret void 78} 79 80; Test the next offset up, which requires separate address logic, 81define void @f9(<16 x i8> %val, <16 x i8> *%base) { 82; CHECK-LABEL: f9: 83; CHECK: aghi %r2, 4096 84; CHECK: vst %v24, 0(%r2), 3 85; CHECK: br %r14 86 %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256 87 store <16 x i8> %val, <16 x i8> *%ptr 88 ret void 89} 90 91; Test negative offsets, which also require separate address logic, 92define void @f10(<16 x i8> %val, <16 x i8> *%base) { 93; CHECK-LABEL: f10: 94; CHECK: aghi %r2, -16 95; CHECK: vst %v24, 0(%r2), 3 96; CHECK: br %r14 97 %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1 98 store <16 x i8> %val, <16 x i8> *%ptr 99 ret void 100} 101 102; Check that indexes are allowed. 103define void @f11(<16 x i8> %val, i8 *%base, i64 %index) { 104; CHECK-LABEL: f11: 105; CHECK: vst %v24, 0(%r3,%r2) 106; CHECK: br %r14 107 %addr = getelementptr i8, i8 *%base, i64 %index 108 %ptr = bitcast i8 *%addr to <16 x i8> * 109 store <16 x i8> %val, <16 x i8> *%ptr, align 1 110 ret void 111} 112 113; Test v2i8 stores. 114define void @f12(<2 x i8> %val, <2 x i8> *%ptr) { 115; CHECK-LABEL: f12: 116; CHECK: vsteh %v24, 0(%r2), 0 117; CHECK: br %r14 118 store <2 x i8> %val, <2 x i8> *%ptr 119 ret void 120} 121 122; Test v4i8 stores. 123define void @f13(<4 x i8> %val, <4 x i8> *%ptr) { 124; CHECK-LABEL: f13: 125; CHECK: vstef %v24, 0(%r2) 126; CHECK: br %r14 127 store <4 x i8> %val, <4 x i8> *%ptr 128 ret void 129} 130 131; Test v8i8 stores. 132define void @f14(<8 x i8> %val, <8 x i8> *%ptr) { 133; CHECK-LABEL: f14: 134; CHECK: vsteg %v24, 0(%r2) 135; CHECK: br %r14 136 store <8 x i8> %val, <8 x i8> *%ptr 137 ret void 138} 139 140; Test v2i16 stores. 141define void @f15(<2 x i16> %val, <2 x i16> *%ptr) { 142; CHECK-LABEL: f15: 143; CHECK: vstef %v24, 0(%r2), 0 144; CHECK: br %r14 145 store <2 x i16> %val, <2 x i16> *%ptr 146 ret void 147} 148 149; Test v4i16 stores. 150define void @f16(<4 x i16> %val, <4 x i16> *%ptr) { 151; CHECK-LABEL: f16: 152; CHECK: vsteg %v24, 0(%r2) 153; CHECK: br %r14 154 store <4 x i16> %val, <4 x i16> *%ptr 155 ret void 156} 157 158; Test v2i32 stores. 159define void @f17(<2 x i32> %val, <2 x i32> *%ptr) { 160; CHECK-LABEL: f17: 161; CHECK: vsteg %v24, 0(%r2), 0 162; CHECK: br %r14 163 store <2 x i32> %val, <2 x i32> *%ptr 164 ret void 165} 166 167; Test v2f32 stores. 168define void @f18(<2 x float> %val, <2 x float> *%ptr) { 169; CHECK-LABEL: f18: 170; CHECK: vsteg %v24, 0(%r2), 0 171; CHECK: br %r14 172 store <2 x float> %val, <2 x float> *%ptr 173 ret void 174} 175 176; Test quadword-aligned stores. 177define void @f19(<16 x i8> %val, <16 x i8> *%ptr) { 178; CHECK-LABEL: f19: 179; CHECK: vst %v24, 0(%r2), 4 180; CHECK: br %r14 181 store <16 x i8> %val, <16 x i8> *%ptr, align 16 182 ret void 183} 184 185