1; Test vector zero-extending loads. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5; Test a v16i1->v16i8 extension. 6define <16 x i8> @f1(<16 x i1> *%ptr) { 7; No expected output, but must compile. 8 %val = load <16 x i1>, <16 x i1> *%ptr 9 %ret = zext <16 x i1> %val to <16 x i8> 10 ret <16 x i8> %ret 11} 12 13; Test a v8i1->v8i16 extension. 14define <8 x i16> @f2(<8 x i1> *%ptr) { 15; No expected output, but must compile. 16 %val = load <8 x i1>, <8 x i1> *%ptr 17 %ret = zext <8 x i1> %val to <8 x i16> 18 ret <8 x i16> %ret 19} 20 21; Test a v8i8->v8i16 extension. 22define <8 x i16> @f3(<8 x i8> *%ptr) { 23; CHECK-LABEL: f3: 24; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) 25; CHECK: vuplhb %v24, [[REG1]] 26; CHECK: br %r14 27 %val = load <8 x i8>, <8 x i8> *%ptr 28 %ret = zext <8 x i8> %val to <8 x i16> 29 ret <8 x i16> %ret 30} 31 32; Test a v4i1->v4i32 extension. 33define <4 x i32> @f4(<4 x i1> *%ptr) { 34; No expected output, but must compile. 35 %val = load <4 x i1>, <4 x i1> *%ptr 36 %ret = zext <4 x i1> %val to <4 x i32> 37 ret <4 x i32> %ret 38} 39 40; Test a v4i8->v4i32 extension. 41define <4 x i32> @f5(<4 x i8> *%ptr) { 42; CHECK-LABEL: f5: 43; CHECK: larl %r1, .LCPI4_0 44; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2) 45; CHECK: vl %v1, 0(%r1), 3 46; CHECK: vperm %v24, %v1, [[REG1]], %v1 47; CHECK: br %r14 48 %val = load <4 x i8>, <4 x i8> *%ptr 49 %ret = zext <4 x i8> %val to <4 x i32> 50 ret <4 x i32> %ret 51} 52 53; Test a v4i16->v4i32 extension. 54define <4 x i32> @f6(<4 x i16> *%ptr) { 55; CHECK-LABEL: f6: 56; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) 57; CHECK: vuplhh %v24, [[REG1]] 58; CHECK: br %r14 59 %val = load <4 x i16>, <4 x i16> *%ptr 60 %ret = zext <4 x i16> %val to <4 x i32> 61 ret <4 x i32> %ret 62} 63 64; Test a v2i1->v2i64 extension. 65define <2 x i64> @f7(<2 x i1> *%ptr) { 66; No expected output, but must compile. 67 %val = load <2 x i1>, <2 x i1> *%ptr 68 %ret = zext <2 x i1> %val to <2 x i64> 69 ret <2 x i64> %ret 70} 71 72; Test a v2i8->v2i64 extension. 73define <2 x i64> @f8(<2 x i8> *%ptr) { 74; CHECK-LABEL: f8: 75; CHECK: larl %r1, .LCPI7_0 76; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2) 77; CHECK: vl %v1, 0(%r1), 3 78; CHECK: vperm %v24, %v1, [[REG1]], %v1 79; CHECK: br %r14 80 %val = load <2 x i8>, <2 x i8> *%ptr 81 %ret = zext <2 x i8> %val to <2 x i64> 82 ret <2 x i64> %ret 83} 84 85; Test a v2i16->v2i64 extension. 86define <2 x i64> @f9(<2 x i16> *%ptr) { 87; CHECK-LABEL: f9: 88; CHECK: larl %r1, .LCPI8_0 89; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2) 90; CHECK: vl %v1, 0(%r1), 3 91; CHECK: vperm %v24, %v1, [[REG1]], %v1 92; CHECK: br %r14 93 %val = load <2 x i16>, <2 x i16> *%ptr 94 %ret = zext <2 x i16> %val to <2 x i64> 95 ret <2 x i64> %ret 96} 97 98; Test a v2i32->v2i64 extension. 99define <2 x i64> @f10(<2 x i32> *%ptr) { 100; CHECK-LABEL: f10: 101; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) 102; CHECK: vuplhf %v24, [[REG1]] 103; CHECK: br %r14 104 %val = load <2 x i32>, <2 x i32> *%ptr 105 %ret = zext <2 x i32> %val to <2 x i64> 106 ret <2 x i64> %ret 107} 108