1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=thumb-eabi -mattr=+v6 | FileCheck %s --check-prefixes=THUMBV6 3 4define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 { 5; THUMBV6-LABEL: muloti_test: 6; THUMBV6: @ %bb.0: @ %start 7; THUMBV6-NEXT: .save {r4, r5, r6, r7, lr} 8; THUMBV6-NEXT: push {r4, r5, r6, r7, lr} 9; THUMBV6-NEXT: .pad #68 10; THUMBV6-NEXT: sub sp, #68 11; THUMBV6-NEXT: mov r4, r3 12; THUMBV6-NEXT: str r2, [sp, #56] @ 4-byte Spill 13; THUMBV6-NEXT: mov r6, r0 14; THUMBV6-NEXT: movs r5, #0 15; THUMBV6-NEXT: str r5, [sp, #12] 16; THUMBV6-NEXT: str r5, [sp, #8] 17; THUMBV6-NEXT: ldr r0, [sp, #100] 18; THUMBV6-NEXT: str r0, [sp, #28] @ 4-byte Spill 19; THUMBV6-NEXT: str r0, [sp, #4] 20; THUMBV6-NEXT: ldr r0, [sp, #96] 21; THUMBV6-NEXT: str r0, [sp, #64] @ 4-byte Spill 22; THUMBV6-NEXT: str r0, [sp] 23; THUMBV6-NEXT: mov r0, r2 24; THUMBV6-NEXT: mov r1, r3 25; THUMBV6-NEXT: mov r2, r5 26; THUMBV6-NEXT: mov r3, r5 27; THUMBV6-NEXT: bl __multi3 28; THUMBV6-NEXT: str r2, [sp, #48] @ 4-byte Spill 29; THUMBV6-NEXT: str r3, [sp, #52] @ 4-byte Spill 30; THUMBV6-NEXT: str r6, [sp, #44] @ 4-byte Spill 31; THUMBV6-NEXT: stm r6!, {r0, r1} 32; THUMBV6-NEXT: ldr r2, [sp, #104] 33; THUMBV6-NEXT: str r2, [sp, #60] @ 4-byte Spill 34; THUMBV6-NEXT: mov r0, r4 35; THUMBV6-NEXT: mov r1, r5 36; THUMBV6-NEXT: mov r3, r5 37; THUMBV6-NEXT: bl __aeabi_lmul 38; THUMBV6-NEXT: str r0, [sp, #36] @ 4-byte Spill 39; THUMBV6-NEXT: mov r7, r1 40; THUMBV6-NEXT: subs r0, r1, #1 41; THUMBV6-NEXT: sbcs r7, r0 42; THUMBV6-NEXT: ldr r6, [sp, #108] 43; THUMBV6-NEXT: mov r0, r6 44; THUMBV6-NEXT: mov r1, r5 45; THUMBV6-NEXT: ldr r2, [sp, #56] @ 4-byte Reload 46; THUMBV6-NEXT: mov r3, r5 47; THUMBV6-NEXT: bl __aeabi_lmul 48; THUMBV6-NEXT: subs r2, r1, #1 49; THUMBV6-NEXT: sbcs r1, r2 50; THUMBV6-NEXT: subs r2, r4, #1 51; THUMBV6-NEXT: sbcs r4, r2 52; THUMBV6-NEXT: str r6, [sp, #40] @ 4-byte Spill 53; THUMBV6-NEXT: subs r2, r6, #1 54; THUMBV6-NEXT: sbcs r6, r2 55; THUMBV6-NEXT: ands r6, r4 56; THUMBV6-NEXT: orrs r6, r1 57; THUMBV6-NEXT: orrs r6, r7 58; THUMBV6-NEXT: ldr r1, [sp, #36] @ 4-byte Reload 59; THUMBV6-NEXT: adds r4, r0, r1 60; THUMBV6-NEXT: ldr r0, [sp, #60] @ 4-byte Reload 61; THUMBV6-NEXT: mov r1, r5 62; THUMBV6-NEXT: ldr r2, [sp, #56] @ 4-byte Reload 63; THUMBV6-NEXT: mov r3, r5 64; THUMBV6-NEXT: bl __aeabi_lmul 65; THUMBV6-NEXT: str r0, [sp, #36] @ 4-byte Spill 66; THUMBV6-NEXT: adds r0, r1, r4 67; THUMBV6-NEXT: str r0, [sp, #32] @ 4-byte Spill 68; THUMBV6-NEXT: mov r0, r5 69; THUMBV6-NEXT: adcs r0, r5 70; THUMBV6-NEXT: orrs r0, r6 71; THUMBV6-NEXT: str r0, [sp, #24] @ 4-byte Spill 72; THUMBV6-NEXT: ldr r4, [sp, #88] 73; THUMBV6-NEXT: ldr r7, [sp, #28] @ 4-byte Reload 74; THUMBV6-NEXT: mov r0, r7 75; THUMBV6-NEXT: mov r1, r5 76; THUMBV6-NEXT: mov r2, r4 77; THUMBV6-NEXT: mov r3, r5 78; THUMBV6-NEXT: bl __aeabi_lmul 79; THUMBV6-NEXT: str r0, [sp, #20] @ 4-byte Spill 80; THUMBV6-NEXT: mov r6, r1 81; THUMBV6-NEXT: subs r0, r1, #1 82; THUMBV6-NEXT: sbcs r6, r0 83; THUMBV6-NEXT: ldr r0, [sp, #92] 84; THUMBV6-NEXT: str r0, [sp, #56] @ 4-byte Spill 85; THUMBV6-NEXT: mov r1, r5 86; THUMBV6-NEXT: ldr r2, [sp, #64] @ 4-byte Reload 87; THUMBV6-NEXT: mov r3, r5 88; THUMBV6-NEXT: bl __aeabi_lmul 89; THUMBV6-NEXT: str r0, [sp, #16] @ 4-byte Spill 90; THUMBV6-NEXT: subs r2, r1, #1 91; THUMBV6-NEXT: sbcs r1, r2 92; THUMBV6-NEXT: subs r2, r7, #1 93; THUMBV6-NEXT: sbcs r7, r2 94; THUMBV6-NEXT: mov r3, r7 95; THUMBV6-NEXT: ldr r7, [sp, #56] @ 4-byte Reload 96; THUMBV6-NEXT: subs r2, r7, #1 97; THUMBV6-NEXT: sbcs r7, r2 98; THUMBV6-NEXT: ands r7, r3 99; THUMBV6-NEXT: orrs r7, r1 100; THUMBV6-NEXT: orrs r7, r6 101; THUMBV6-NEXT: ldr r0, [sp, #20] @ 4-byte Reload 102; THUMBV6-NEXT: ldr r1, [sp, #16] @ 4-byte Reload 103; THUMBV6-NEXT: adds r6, r1, r0 104; THUMBV6-NEXT: mov r0, r4 105; THUMBV6-NEXT: mov r1, r5 106; THUMBV6-NEXT: ldr r2, [sp, #64] @ 4-byte Reload 107; THUMBV6-NEXT: mov r3, r5 108; THUMBV6-NEXT: bl __aeabi_lmul 109; THUMBV6-NEXT: adds r1, r1, r6 110; THUMBV6-NEXT: mov r2, r5 111; THUMBV6-NEXT: adcs r2, r5 112; THUMBV6-NEXT: orrs r2, r7 113; THUMBV6-NEXT: ldr r6, [sp, #60] @ 4-byte Reload 114; THUMBV6-NEXT: ldr r3, [sp, #40] @ 4-byte Reload 115; THUMBV6-NEXT: orrs r6, r3 116; THUMBV6-NEXT: subs r3, r6, #1 117; THUMBV6-NEXT: sbcs r6, r3 118; THUMBV6-NEXT: ldr r3, [sp, #56] @ 4-byte Reload 119; THUMBV6-NEXT: orrs r4, r3 120; THUMBV6-NEXT: subs r3, r4, #1 121; THUMBV6-NEXT: sbcs r4, r3 122; THUMBV6-NEXT: ands r4, r6 123; THUMBV6-NEXT: orrs r4, r2 124; THUMBV6-NEXT: ldr r2, [sp, #24] @ 4-byte Reload 125; THUMBV6-NEXT: orrs r4, r2 126; THUMBV6-NEXT: ldr r2, [sp, #36] @ 4-byte Reload 127; THUMBV6-NEXT: adds r0, r0, r2 128; THUMBV6-NEXT: ldr r2, [sp, #32] @ 4-byte Reload 129; THUMBV6-NEXT: adcs r1, r2 130; THUMBV6-NEXT: ldr r2, [sp, #48] @ 4-byte Reload 131; THUMBV6-NEXT: adds r0, r2, r0 132; THUMBV6-NEXT: ldr r2, [sp, #44] @ 4-byte Reload 133; THUMBV6-NEXT: str r0, [r2, #8] 134; THUMBV6-NEXT: ldr r0, [sp, #52] @ 4-byte Reload 135; THUMBV6-NEXT: adcs r1, r0 136; THUMBV6-NEXT: str r1, [r2, #12] 137; THUMBV6-NEXT: adcs r5, r5 138; THUMBV6-NEXT: orrs r5, r4 139; THUMBV6-NEXT: movs r0, #1 140; THUMBV6-NEXT: ands r0, r5 141; THUMBV6-NEXT: strb r0, [r2, #16] 142; THUMBV6-NEXT: add sp, #68 143; THUMBV6-NEXT: pop {r4, r5, r6, r7, pc} 144start: 145 %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2 146 %1 = extractvalue { i128, i1 } %0, 0 147 %2 = extractvalue { i128, i1 } %0, 1 148 %3 = zext i1 %2 to i8 149 %4 = insertvalue { i128, i8 } undef, i128 %1, 0 150 %5 = insertvalue { i128, i8 } %4, i8 %3, 1 151 ret { i128, i8 } %5 152} 153 154; Function Attrs: nounwind readnone speculatable 155declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1 156 157attributes #0 = { nounwind readnone uwtable } 158attributes #1 = { nounwind readnone speculatable } 159attributes #2 = { nounwind } 160