1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 define hidden i32 @max_min_add_reduce(i8* %input_1_vect, i8* %input_2_vect, i32 %input_1_offset, i32 %input_2_offset, i32* %output, i32 %out_offset, i32 %out_mult, i32 %out_shift, i32 %out_activation_min, i32 %out_activation_max, i32 %block_size) local_unnamed_addr #0 { 6 entry: 7 %add = add i32 %block_size, 3 8 %div = lshr i32 %add, 2 9 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %div) 10 br i1 %0, label %for.body.lr.ph, label %for.cond.cleanup 11 12 for.body.lr.ph: ; preds = %entry 13 %.splatinsert.i41 = insertelement <4 x i32> undef, i32 %out_activation_min, i32 0 14 %.splat.i42 = shufflevector <4 x i32> %.splatinsert.i41, <4 x i32> undef, <4 x i32> zeroinitializer 15 %.splatinsert.i = insertelement <4 x i32> undef, i32 %out_activation_max, i32 0 16 %.splat.i = shufflevector <4 x i32> %.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer 17 %scevgep = getelementptr i32, i32* %output, i32 -1 18 br label %for.body 19 20 for.cond.cleanup: ; preds = %for.body, %entry 21 ret i32 0 22 23 for.body: ; preds = %for.body, %for.body.lr.ph 24 %lsr.iv3 = phi i32 [ %lsr.iv.next, %for.body ], [ %div, %for.body.lr.ph ] 25 %lsr.iv = phi i32* [ %scevgep1, %for.body ], [ %scevgep, %for.body.lr.ph ] 26 %input_1_vect.addr.052 = phi i8* [ %input_1_vect, %for.body.lr.ph ], [ %add.ptr, %for.body ] 27 %input_2_vect.addr.051 = phi i8* [ %input_2_vect, %for.body.lr.ph ], [ %add.ptr14, %for.body ] 28 %num_elements.049 = phi i32 [ %block_size, %for.body.lr.ph ], [ %sub, %for.body ] 29 %input_2_cast = bitcast i8* %input_2_vect.addr.051 to <4 x i32>* 30 %input_1_cast = bitcast i8* %input_1_vect.addr.052 to <4 x i32>* 31 %scevgep2 = getelementptr i32, i32* %lsr.iv, i32 1 32 %pred = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %num_elements.049) 33 %load.1 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %input_1_cast, i32 4, <4 x i1> %pred, <4 x i32> undef) 34 %insert.input_1_offset = insertelement <4 x i32> undef, i32 %input_1_offset, i32 0 35 %splat.input_1_offset = shufflevector <4 x i32> %insert.input_1_offset, <4 x i32> undef, <4 x i32> zeroinitializer 36 %insert.input_2_offset = insertelement <4 x i32> undef, i32 %input_2_offset, i32 0 37 %splat.input_2_offset = shufflevector <4 x i32> %insert.input_2_offset, <4 x i32> undef, <4 x i32> zeroinitializer 38 %add.1 = add <4 x i32> %load.1, %splat.input_1_offset 39 %load.2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %input_2_cast, i32 4, <4 x i1> %pred, <4 x i32> undef) 40 %add.2 = add <4 x i32> %load.2, %splat.input_2_offset 41 %mul = mul <4 x i32> %add.1, %add.2 42 %insert.output = insertelement <4 x i32> undef, i32 %out_offset, i32 0 43 %splat.output = shufflevector <4 x i32> %insert.output, <4 x i32> undef, <4 x i32> zeroinitializer 44 %add7 = add <4 x i32> %mul, %splat.output 45 %max = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %add7, <4 x i32> %.splat.i42, i32 1, <4 x i1> %pred, <4 x i32> undef) 46 %min = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %max, <4 x i32> %.splat.i, i32 1, <4 x i1> %pred, <4 x i32> undef) 47 %reduce = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %min) 48 store i32 %reduce, i32* %scevgep2 49 %add.ptr = getelementptr inbounds i8, i8* %input_1_vect.addr.052, i32 4 50 %add.ptr14 = getelementptr inbounds i8, i8* %input_2_vect.addr.051, i32 4 51 %sub = add i32 %num_elements.049, -4 52 %iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv3, i32 1) 53 %cmp = icmp ne i32 %iv.next, 0 54 %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1 55 %lsr.iv.next = add i32 %lsr.iv3, -1 56 br i1 %cmp, label %for.body, label %for.cond.cleanup 57 } 58 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 59 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2 60 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #3 61 declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 62 declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 63 declare i1 @llvm.test.set.loop.iterations.i32(i32) #4 64 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #4 65 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #5 66 67... 68--- 69name: max_min_add_reduce 70alignment: 2 71exposesReturnsTwice: false 72legalized: false 73regBankSelected: false 74selected: false 75failedISel: false 76tracksRegLiveness: true 77hasWinCFI: false 78registers: [] 79liveins: 80 - { reg: '$r0', virtual-reg: '' } 81 - { reg: '$r1', virtual-reg: '' } 82 - { reg: '$r2', virtual-reg: '' } 83 - { reg: '$r3', virtual-reg: '' } 84frameInfo: 85 isFrameAddressTaken: false 86 isReturnAddressTaken: false 87 hasStackMap: false 88 hasPatchPoint: false 89 stackSize: 24 90 offsetAdjustment: 0 91 maxAlignment: 4 92 adjustsStack: false 93 hasCalls: false 94 stackProtector: '' 95 maxCallFrameSize: 0 96 cvBytesOfCalleeSavedRegisters: 0 97 hasOpaqueSPAdjustment: false 98 hasVAStart: false 99 hasMustTailInVarArgFunc: false 100 localFrameSize: 0 101 savePoint: '' 102 restorePoint: '' 103fixedStack: 104 - { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default, 105 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 106 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 107 - { id: 1, type: default, offset: 20, size: 4, alignment: 4, stack-id: default, 108 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 109 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 110 - { id: 2, type: default, offset: 16, size: 4, alignment: 8, stack-id: default, 111 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 112 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 113 - { id: 3, type: default, offset: 12, size: 4, alignment: 4, stack-id: default, 114 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 115 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 116 - { id: 4, type: default, offset: 8, size: 4, alignment: 8, stack-id: default, 117 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 118 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 119 - { id: 5, type: default, offset: 4, size: 4, alignment: 4, stack-id: default, 120 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 121 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 122 - { id: 6, type: default, offset: 0, size: 4, alignment: 8, stack-id: default, 123 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 124 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 125stack: 126 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 127 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 128 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 129 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 130 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 131 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 132 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 133 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 134 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 135 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 136 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 137 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 138 - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 139 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 140 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 141 - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 142 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 143 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 144callSites: [] 145constants: [] 146machineFunctionInfo: {} 147body: | 148 ; CHECK-LABEL: name: max_min_add_reduce 149 ; CHECK: bb.0.entry: 150 ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) 151 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8 152 ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr 153 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 154 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 155 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -8 156 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -12 157 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -16 158 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -20 159 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -24 160 ; CHECK: renamable $r12 = t2LDRi12 $sp, 48, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.6, align 8) 161 ; CHECK: renamable $r5 = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 162 ; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14 /* CC::al */, $noreg 163 ; CHECK: dead $lr = t2WLS renamable $r7, %bb.3 164 ; CHECK: bb.1.for.body.lr.ph: 165 ; CHECK: successors: %bb.2(0x80000000) 166 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $r12 167 ; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5) 168 ; CHECK: $r4 = tMOVr killed $r7, 14 /* CC::al */, $noreg 169 ; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1) 170 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 171 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1 172 ; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14 /* CC::al */, $noreg 173 ; CHECK: bb.2.for.body: 174 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 175 ; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12 176 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg 177 ; CHECK: MVE_VPST 8, implicit $vpr 178 ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 16 from %ir.input_2_cast, align 4) 179 ; CHECK: MVE_VPST 8, implicit $vpr 180 ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4) 181 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 182 ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 183 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 184 ; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 185 ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 186 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2 187 ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 188 ; CHECK: MVE_VPST 4, implicit $vpr 189 ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 190 ; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2 191 ; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg 192 ; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep2) 193 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 194 ; CHECK: bb.3.for.cond.cleanup: 195 ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 196 ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 197 bb.0.entry: 198 successors: %bb.1(0x40000000), %bb.3(0x40000000) 199 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr 200 201 $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr 202 frame-setup CFI_INSTRUCTION def_cfa_offset 24 203 frame-setup CFI_INSTRUCTION offset $lr, -4 204 frame-setup CFI_INSTRUCTION offset $r8, -8 205 frame-setup CFI_INSTRUCTION offset $r7, -12 206 frame-setup CFI_INSTRUCTION offset $r6, -16 207 frame-setup CFI_INSTRUCTION offset $r5, -20 208 frame-setup CFI_INSTRUCTION offset $r4, -24 209 renamable $r12 = t2LDRi12 $sp, 48, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) 210 renamable $r5 = t2ADDri renamable $r12, 3, 14, $noreg, $noreg 211 renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14, $noreg 212 t2WhileLoopStart renamable $r7, %bb.3, implicit-def dead $cpsr 213 tB %bb.1, 14, $noreg 214 215 bb.1.for.body.lr.ph: 216 successors: %bb.2(0x80000000) 217 liveins: $r0, $r1, $r2, $r3, $r7, $r12 218 219 $r6, $r5 = t2LDRDi8 $sp, 40, 14, $noreg :: (load 4 from %fixed-stack.2, align 8), (load 4 from %fixed-stack.1) 220 $r4 = tMOVr killed $r7, 14, $noreg 221 $r7, $r8 = t2LDRDi8 $sp, 24, 14, $noreg :: (load 4 from %fixed-stack.6, align 8), (load 4 from %fixed-stack.5) 222 renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 223 renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1 224 renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14, $noreg 225 226 bb.2.for.body: 227 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 228 liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12 229 230 renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg 231 MVE_VPST 8, implicit $vpr 232 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 16 from %ir.input_2_cast, align 4) 233 MVE_VPST 8, implicit $vpr 234 renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4) 235 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 236 renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 237 $lr = tMOVr $r4, 14, $noreg 238 renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 239 renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14, $noreg 240 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2 241 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 242 MVE_VPST 4, implicit $vpr 243 renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 244 renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2 245 renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg 246 early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14, $noreg :: (store 4 into %ir.scevgep2) 247 renamable $lr = t2LoopDec killed renamable $lr, 1 248 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 249 tB %bb.3, 14, $noreg 250 251 bb.3.for.cond.cleanup: 252 $r0, dead $cpsr = tMOVi8 0, 14, $noreg 253 $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 254 255... 256