1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s 3 4--- | 5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 6 target triple = "thumbv8.1m.main" 7 8 define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) { 9 entry: 10 %scevgep = getelementptr i32, i32* %q, i32 -1 11 %scevgep3 = getelementptr i32, i32* %p, i32 -1 12 %start = call i32 @llvm.start.loop.iterations.i32(i32 %n) 13 br label %while.body 14 15 while.body: ; preds = %while.body, %entry 16 %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ] 17 %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ] 18 %0 = phi i32 [ %start, %entry ], [ %2, %while.body ] 19 %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1 20 %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1 21 %1 = load i32, i32* %scevgep6, align 4 22 store i32 %1, i32* %scevgep2, align 4 23 %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1 24 %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1 25 %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) 26 %3 = icmp ne i32 %2, 0 27 br i1 %3, label %while.body, label %while.end 28 29 while.end: ; preds = %while.body 30 ret i32 0 31 } 32 33 declare i32 @llvm.start.loop.iterations.i32(i32) #0 34 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 35 36 attributes #0 = { noduplicate nounwind } 37 attributes #1 = { nounwind } 38 39... 40--- 41name: do_copy 42alignment: 2 43exposesReturnsTwice: false 44legalized: false 45regBankSelected: false 46selected: false 47failedISel: false 48tracksRegLiveness: true 49hasWinCFI: false 50registers: [] 51liveins: 52 - { reg: '$r0', virtual-reg: '' } 53 - { reg: '$r1', virtual-reg: '' } 54 - { reg: '$r2', virtual-reg: '' } 55frameInfo: 56 isFrameAddressTaken: false 57 isReturnAddressTaken: false 58 hasStackMap: false 59 hasPatchPoint: false 60 stackSize: 8 61 offsetAdjustment: 0 62 maxAlignment: 4 63 adjustsStack: false 64 hasCalls: false 65 stackProtector: '' 66 maxCallFrameSize: 0 67 cvBytesOfCalleeSavedRegisters: 0 68 hasOpaqueSPAdjustment: false 69 hasVAStart: false 70 hasMustTailInVarArgFunc: false 71 localFrameSize: 0 72 savePoint: '' 73 restorePoint: '' 74fixedStack: [] 75stack: 76 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 77 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 78 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 79 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 80 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 81 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 82callSites: [] 83constants: [] 84machineFunctionInfo: {} 85body: | 86 ; CHECK-LABEL: name: do_copy 87 ; CHECK: bb.0.entry: 88 ; CHECK: successors: %bb.1(0x80000000) 89 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 90 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 91 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 92 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 93 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 94 ; CHECK: dead $lr = t2DLS $r0 95 ; CHECK: $lr = tMOVr killed $r0, 14 /* CC::al */, $noreg 96 ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg 97 ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg 98 ; CHECK: bb.1.while.body: 99 ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) 100 ; CHECK: liveins: $lr, $r0, $r1 101 ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep6) 102 ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep2) 103 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 104 ; CHECK: bb.2.while.end: 105 ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 106 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 107 bb.0.entry: 108 successors: %bb.1(0x80000000) 109 liveins: $r0, $r1, $r2, $r7, $lr 110 111 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 112 frame-setup CFI_INSTRUCTION def_cfa_offset 8 113 frame-setup CFI_INSTRUCTION offset $lr, -4 114 frame-setup CFI_INSTRUCTION offset $r7, -8 115 $lr = t2DoLoopStart $r0 116 $lr = tMOVr killed $r0, 14, $noreg 117 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg 118 renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg 119 120 bb.1.while.body: 121 successors: %bb.1(0x7c000000), %bb.2(0x04000000) 122 liveins: $lr, $r0, $r1 123 124 renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) 125 early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) 126 renamable $lr = t2LoopDec killed renamable $lr, 1 127 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr 128 tB %bb.2, 14, $noreg 129 130 bb.2.while.end: 131 $r0, dead $cpsr = tMOVi8 0, 14, $noreg 132 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 133 134... 135