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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -run-pass=arm-low-overhead-loops -o - --verify-machineinstrs | FileCheck %s
3
4--- |
5  define dso_local arm_aapcs_vfpcc zeroext i8 @non_masked_load(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
6  entry:
7    %cmp11 = icmp eq i32 %N, 0
8    %0 = add i32 %N, 15
9    %1 = lshr i32 %0, 4
10    %2 = shl nuw i32 %1, 4
11    %3 = add i32 %2, -16
12    %4 = lshr i32 %3, 4
13    %5 = add nuw nsw i32 %4, 1
14    br i1 %cmp11, label %for.cond.cleanup, label %vector.ph
15
16  vector.ph:                                        ; preds = %entry
17    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
18    %6 = shl i32 %4, 3
19    %7 = sub i32 %N, %6
20    br label %vector.body
21
22  vector.body:                                      ; preds = %vector.body, %vector.ph
23    %lsr.iv20 = phi i8* [ %scevgep21, %vector.body ], [ %b, %vector.ph ]
24    %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
25    %vec.phi = phi <16 x i8> [ zeroinitializer, %vector.ph ], [ %13, %vector.body ]
26    %8 = phi i32 [ %start, %vector.ph ], [ %14, %vector.body ]
27    %9 = phi i32 [ %N, %vector.ph ], [ %11, %vector.body ]
28    %lsr.iv2022 = bitcast i8* %lsr.iv20 to <16 x i8>*
29    %lsr.iv19 = bitcast i8* %lsr.iv to <16 x i8>*
30    %10 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %9)
31    %11 = sub i32 %9, 16
32    %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv19, i32 1, <16 x i1> %10, <16 x i8> undef)
33    %wide.load16 = load <16 x i8>, <16 x i8>* %lsr.iv2022
34    %12 = add <16 x i8> %wide.masked.load, %vec.phi
35    %13 = add <16 x i8> %12, %wide.load16
36    %scevgep = getelementptr i8, i8* %lsr.iv, i32 16
37    %scevgep21 = getelementptr i8, i8* %lsr.iv20, i32 16
38    %14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %8, i32 1)
39    %15 = icmp ne i32 %14, 0
40    br i1 %15, label %vector.body, label %middle.block
41
42  middle.block:                                     ; preds = %vector.body
43    %vec.phi.lcssa = phi <16 x i8> [ %vec.phi, %vector.body ]
44    %.lcssa = phi <16 x i8> [ %13, %vector.body ]
45    %16 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7)
46    %17 = select <16 x i1> %16, <16 x i8> %.lcssa, <16 x i8> %vec.phi.lcssa
47    %18 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %17)
48    br label %for.cond.cleanup
49
50  for.cond.cleanup:                                 ; preds = %middle.block, %entry
51    %res.0.lcssa = phi i8 [ 0, %entry ], [ %18, %middle.block ]
52    ret i8 %res.0.lcssa
53  }
54
55  declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>) #1
56  declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>) #2
57  declare i32 @llvm.start.loop.iterations.i32(i32) #3
58  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
59  declare <16 x i1> @llvm.arm.mve.vctp8(i32) #4
60
61...
62---
63name:            non_masked_load
64alignment:       2
65exposesReturnsTwice: false
66legalized:       false
67regBankSelected: false
68selected:        false
69failedISel:      false
70tracksRegLiveness: true
71hasWinCFI:       false
72registers:       []
73liveins:
74  - { reg: '$r0', virtual-reg: '' }
75  - { reg: '$r1', virtual-reg: '' }
76  - { reg: '$r2', virtual-reg: '' }
77frameInfo:
78  isFrameAddressTaken: false
79  isReturnAddressTaken: false
80  hasStackMap:     false
81  hasPatchPoint:   false
82  stackSize:       8
83  offsetAdjustment: 0
84  maxAlignment:    4
85  adjustsStack:    false
86  hasCalls:        false
87  stackProtector:  ''
88  maxCallFrameSize: 0
89  cvBytesOfCalleeSavedRegisters: 0
90  hasOpaqueSPAdjustment: false
91  hasVAStart:      false
92  hasMustTailInVarArgFunc: false
93  localFrameSize:  0
94  savePoint:       ''
95  restorePoint:    ''
96fixedStack:      []
97stack:
98  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
99      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
100      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
101  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
102      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
103      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
104callSites:       []
105constants:       []
106machineFunctionInfo: {}
107body:             |
108  ; CHECK-LABEL: name: non_masked_load
109  ; CHECK: bb.0.entry:
110  ; CHECK:   successors: %bb.1(0x80000000)
111  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
112  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
113  ; CHECK:   t2IT 0, 2, implicit-def $itstate
114  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
115  ; CHECK:   renamable $r0 = tUXTB killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
116  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
117  ; CHECK: bb.1.vector.ph:
118  ; CHECK:   successors: %bb.2(0x80000000)
119  ; CHECK:   liveins: $lr, $r0, $r1, $r2
120  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
121  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
122  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
123  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
124  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
125  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
126  ; CHECK:   renamable $r3 = t2ADDri renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg
127  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
128  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg
129  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
130  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
131  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg
132  ; CHECK:   renamable $r3 = t2LSRri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
133  ; CHECK:   renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14 /* CC::al */, $noreg, $noreg
134  ; CHECK:   $lr = t2DLS killed renamable $lr
135  ; CHECK: bb.2.vector.body:
136  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
137  ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r2, $r3
138  ; CHECK:   renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg
139  ; CHECK:   $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1
140  ; CHECK:   MVE_VPST 2, implicit $vpr
141  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv2022, align 1)
142  ; CHECK:   renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg :: (load 16 from %ir.lsr.iv19, align 1)
143  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
144  ; CHECK:   renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2
145  ; CHECK:   renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
146  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
147  ; CHECK: bb.3.middle.block:
148  ; CHECK:   liveins: $q0, $q1, $r3
149  ; CHECK:   renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg
150  ; CHECK:   renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
151  ; CHECK:   renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg
152  ; CHECK:   $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
153  ; CHECK:   renamable $r0 = tUXTB killed renamable $r0, 14 /* CC::al */, $noreg
154  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
155  bb.0.entry:
156    successors: %bb.1(0x80000000)
157    liveins: $r0, $r1, $r2, $lr
158
159    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
160    t2IT 0, 2, implicit-def $itstate
161    renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
162    renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate
163    tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
164
165  bb.1.vector.ph:
166    successors: %bb.2(0x80000000)
167    liveins: $r0, $r1, $r2, $lr
168
169    frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
170    frame-setup CFI_INSTRUCTION def_cfa_offset 8
171    frame-setup CFI_INSTRUCTION offset $lr, -4
172    frame-setup CFI_INSTRUCTION offset $r7, -8
173    $r7 = frame-setup tMOVr $sp, 14, $noreg
174    frame-setup CFI_INSTRUCTION def_cfa_register $r7
175    renamable $r3 = t2ADDri renamable $r2, 15, 14, $noreg, $noreg
176    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
177    renamable $r3 = t2BICri killed renamable $r3, 15, 14, $noreg, $noreg
178    renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg
179    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
180    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14, $noreg, $noreg
181    renamable $r3 = t2LSRri killed renamable $r12, 4, 14, $noreg, $noreg
182    renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14, $noreg, $noreg
183    $lr = t2DoLoopStart renamable $lr
184
185  bb.2.vector.body:
186    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
187    liveins: $lr, $q0, $r0, $r1, $r2, $r3
188
189    renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg
190    $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1
191    MVE_VPST 2, implicit $vpr
192    renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv2022, align 1)
193    renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg :: (load 16 from %ir.lsr.iv19, align 1)
194    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14, $noreg
195    renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2
196    renamable $lr = t2LoopDec killed renamable $lr, 1
197    renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0
198    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
199    tB %bb.3, 14, $noreg
200
201  bb.3.middle.block:
202    liveins: $q0, $q1, $r3
203
204    renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg
205    renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
206    renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg
207    $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr
208    renamable $r0 = tUXTB killed renamable $r0, 14, $noreg
209    tBX_RET 14, $noreg, implicit killed $r0
210
211...
212