1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 define dso_local arm_aapcs_vfpcc void @remove_mov_lr_chain(float* nocapture readonly %pSrc, float* nocapture %pDst, i32 %blockSize) #0 { 6 entry: 7 %cmp5 = icmp eq i32 %blockSize, 0 8 br i1 %cmp5, label %while.end, label %while.body.preheader 9 10 while.body.preheader: ; preds = %entry 11 %min.iters.check = icmp ult i32 %blockSize, 4 12 br i1 %min.iters.check, label %while.body.preheader19, label %vector.memcheck 13 14 vector.memcheck: ; preds = %while.body.preheader 15 %scevgep = getelementptr float, float* %pDst, i32 %blockSize 16 %scevgep12 = getelementptr float, float* %pSrc, i32 %blockSize 17 %bound0 = icmp ugt float* %scevgep12, %pDst 18 %bound1 = icmp ugt float* %scevgep, %pSrc 19 %found.conflict = and i1 %bound0, %bound1 20 %0 = lshr i32 %blockSize, 2 21 %1 = shl nuw i32 %0, 2 22 %2 = add i32 %1, -4 23 %3 = lshr i32 %2, 2 24 %4 = add nuw nsw i32 %3, 1 25 br i1 %found.conflict, label %while.body.preheader19, label %vector.ph 26 27 vector.ph: ; preds = %vector.memcheck 28 %n.vec = and i32 %blockSize, -4 29 %ind.end = sub i32 %blockSize, %n.vec 30 %ind.end15 = getelementptr float, float* %pSrc, i32 %n.vec 31 %ind.end17 = getelementptr float, float* %pDst, i32 %n.vec 32 %scevgep9 = getelementptr float, float* %pDst, i32 -4 33 %scevgep14 = getelementptr float, float* %pSrc, i32 -4 34 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %4) 35 br label %vector.body 36 37 vector.body: ; preds = %vector.body, %vector.ph 38 %lsr.iv15 = phi float* [ %scevgep16, %vector.body ], [ %scevgep14, %vector.ph ] 39 %lsr.iv10 = phi float* [ %scevgep11, %vector.body ], [ %scevgep9, %vector.ph ] 40 %5 = phi i32 [ %start1, %vector.ph ], [ %7, %vector.body ] 41 %lsr.iv1517 = bitcast float* %lsr.iv15 to <4 x float>* 42 %lsr.iv1012 = bitcast float* %lsr.iv10 to <4 x float>* 43 %scevgep18 = getelementptr <4 x float>, <4 x float>* %lsr.iv1517, i32 1 44 %wide.load = load <4 x float>, <4 x float>* %scevgep18, align 4 45 %6 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %wide.load) 46 %scevgep13 = getelementptr <4 x float>, <4 x float>* %lsr.iv1012, i32 1 47 store <4 x float> %6, <4 x float>* %scevgep13, align 4 48 %scevgep11 = getelementptr float, float* %lsr.iv10, i32 4 49 %scevgep16 = getelementptr float, float* %lsr.iv15, i32 4 50 %7 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 51 %8 = icmp ne i32 %7, 0 52 br i1 %8, label %vector.body, label %middle.block 53 54 middle.block: ; preds = %vector.body 55 %cmp.n = icmp eq i32 %n.vec, %blockSize 56 br i1 %cmp.n, label %while.end, label %while.body.preheader19 57 58 while.body.preheader19: ; preds = %middle.block, %vector.memcheck, %while.body.preheader 59 %blkCnt.08.ph = phi i32 [ %blockSize, %vector.memcheck ], [ %blockSize, %while.body.preheader ], [ %ind.end, %middle.block ] 60 %pSrc.addr.07.ph = phi float* [ %pSrc, %vector.memcheck ], [ %pSrc, %while.body.preheader ], [ %ind.end15, %middle.block ] 61 %pDst.addr.06.ph = phi float* [ %pDst, %vector.memcheck ], [ %pDst, %while.body.preheader ], [ %ind.end17, %middle.block ] 62 %scevgep1 = getelementptr float, float* %pSrc.addr.07.ph, i32 -1 63 %scevgep4 = getelementptr float, float* %pDst.addr.06.ph, i32 -1 64 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %blkCnt.08.ph) 65 br label %while.body 66 67 while.body: ; preds = %while.body, %while.body.preheader19 68 %lsr.iv5 = phi float* [ %scevgep6, %while.body ], [ %scevgep4, %while.body.preheader19 ] 69 %lsr.iv = phi float* [ %scevgep2, %while.body ], [ %scevgep1, %while.body.preheader19 ] 70 %9 = phi i32 [ %start2, %while.body.preheader19 ], [ %12, %while.body ] 71 %scevgep3 = getelementptr float, float* %lsr.iv, i32 1 72 %scevgep7 = getelementptr float, float* %lsr.iv5, i32 1 73 %10 = load float, float* %scevgep3, align 4 74 %11 = tail call fast float @llvm.fabs.f32(float %10) 75 store float %11, float* %scevgep7, align 4 76 %scevgep2 = getelementptr float, float* %lsr.iv, i32 1 77 %scevgep6 = getelementptr float, float* %lsr.iv5, i32 1 78 %12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %9, i32 1) 79 %13 = icmp ne i32 %12, 0 80 br i1 %13, label %while.body, label %while.end 81 82 while.end: ; preds = %while.body, %middle.block, %entry 83 ret void 84 } 85 declare float @llvm.fabs.f32(float) 86 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) 87 declare i32 @llvm.start.loop.iterations.i32(i32) 88 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 89 90... 91--- 92name: remove_mov_lr_chain 93alignment: 2 94exposesReturnsTwice: false 95legalized: false 96regBankSelected: false 97selected: false 98failedISel: false 99tracksRegLiveness: true 100hasWinCFI: false 101registers: [] 102liveins: 103 - { reg: '$r0', virtual-reg: '' } 104 - { reg: '$r1', virtual-reg: '' } 105 - { reg: '$r2', virtual-reg: '' } 106frameInfo: 107 isFrameAddressTaken: false 108 isReturnAddressTaken: false 109 hasStackMap: false 110 hasPatchPoint: false 111 stackSize: 16 112 offsetAdjustment: 0 113 maxAlignment: 4 114 adjustsStack: false 115 hasCalls: false 116 stackProtector: '' 117 maxCallFrameSize: 0 118 cvBytesOfCalleeSavedRegisters: 0 119 hasOpaqueSPAdjustment: false 120 hasVAStart: false 121 hasMustTailInVarArgFunc: false 122 localFrameSize: 0 123 savePoint: '' 124 restorePoint: '' 125fixedStack: [] 126stack: 127 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 128 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 129 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 130 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 131 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 132 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 133 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 134 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 135 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 136 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 137 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 138 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 139callSites: [] 140constants: [] 141machineFunctionInfo: {} 142body: | 143 ; CHECK-LABEL: name: remove_mov_lr_chain 144 ; CHECK: bb.0.entry: 145 ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) 146 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7 147 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp 148 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 149 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 150 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 151 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 152 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 153 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 154 ; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr 155 ; CHECK: bb.1.while.body.preheader: 156 ; CHECK: successors: %bb.6(0x40000000), %bb.2(0x40000000) 157 ; CHECK: liveins: $r0, $r1, $r2 158 ; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 159 ; CHECK: tBcc %bb.6, 3 /* CC::lo */, killed $cpsr 160 ; CHECK: bb.2.vector.memcheck: 161 ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000) 162 ; CHECK: liveins: $r0, $r1, $r2 163 ; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg 164 ; CHECK: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr 165 ; CHECK: t2IT 8, 4, implicit-def $itstate 166 ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate 167 ; CHECK: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate 168 ; CHECK: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr 169 ; CHECK: bb.3.vector.ph: 170 ; CHECK: successors: %bb.4(0x80000000) 171 ; CHECK: liveins: $r0, $r1, $r2 172 ; CHECK: renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 173 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 174 ; CHECK: renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg 175 ; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg 176 ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 177 ; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg 178 ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg 179 ; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg 180 ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg 181 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 182 ; CHECK: bb.4.vector.body: 183 ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000) 184 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12 185 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.scevgep18, align 4) 186 ; CHECK: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg 187 ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0 188 ; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4) 189 ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr 190 ; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg 191 ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr 192 ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg 193 ; CHECK: bb.5.middle.block: 194 ; CHECK: successors: %bb.7(0x80000000) 195 ; CHECK: liveins: $r2, $r3, $r4, $r7, $r12 196 ; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr 197 ; CHECK: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg 198 ; CHECK: t2IT 0, 8, implicit-def $itstate 199 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate 200 ; CHECK: tB %bb.7, 14 /* CC::al */, $noreg 201 ; CHECK: bb.6: 202 ; CHECK: successors: %bb.7(0x80000000) 203 ; CHECK: liveins: $r0, $r1, $r2 204 ; CHECK: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg 205 ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg 206 ; CHECK: $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg 207 ; CHECK: bb.7.while.body.preheader19: 208 ; CHECK: successors: %bb.8(0x80000000) 209 ; CHECK: liveins: $lr, $r3, $r12 210 ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg 211 ; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 212 ; CHECK: $lr = t2DLS killed renamable $lr 213 ; CHECK: bb.8.while.body: 214 ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) 215 ; CHECK: liveins: $lr, $r0, $r1 216 ; CHECK: renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep3) 217 ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 218 ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg 219 ; CHECK: VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep7) 220 ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 221 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8 222 ; CHECK: bb.9.while.end: 223 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc 224 bb.0.entry: 225 successors: %bb.9(0x30000000), %bb.1(0x50000000) 226 liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr 227 228 frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp 229 frame-setup CFI_INSTRUCTION def_cfa_offset 16 230 frame-setup CFI_INSTRUCTION offset $lr, -4 231 frame-setup CFI_INSTRUCTION offset $r7, -8 232 frame-setup CFI_INSTRUCTION offset $r5, -12 233 frame-setup CFI_INSTRUCTION offset $r4, -16 234 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr 235 tBcc %bb.9, 0, killed $cpsr 236 237 bb.1.while.body.preheader: 238 successors: %bb.6(0x40000000), %bb.2(0x40000000) 239 liveins: $r0, $r1, $r2 240 241 tCMPi8 renamable $r2, 4, 14, $noreg, implicit-def $cpsr 242 tBcc %bb.6, 3, killed $cpsr 243 244 bb.2.vector.memcheck: 245 successors: %bb.3(0x40000000), %bb.6(0x40000000) 246 liveins: $r0, $r1, $r2 247 248 renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14, $noreg, $noreg 249 tCMPr killed renamable $r3, renamable $r1, 14, $noreg, implicit-def $cpsr 250 t2IT 8, 4, implicit-def $itstate 251 renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8, $cpsr, $noreg, implicit $itstate 252 tCMPr killed renamable $r3, renamable $r0, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate 253 tBcc %bb.6, 8, killed $cpsr 254 255 bb.3.vector.ph: 256 successors: %bb.4(0x80000000) 257 liveins: $r0, $r1, $r2 258 259 renamable $r4 = t2BICri renamable $r2, 3, 14, $noreg, $noreg 260 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg 261 renamable $r12 = t2SUBri renamable $r4, 4, 14, $noreg, $noreg 262 renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14, $noreg 263 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg 264 renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14, $noreg, $noreg 265 $lr = t2DoLoopStart renamable $r3 266 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14, $noreg 267 $r5 = tMOVr killed $r3, 14, $noreg 268 renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14, $noreg, $noreg 269 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14, $noreg 270 271 bb.4.vector.body: 272 successors: %bb.4(0x7c000000), %bb.5(0x04000000) 273 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12 274 275 renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.scevgep18, align 4) 276 $lr = tMOVr killed $r5, 14, $noreg 277 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0 278 renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4) 279 renamable $lr = t2LoopDec killed renamable $lr, 1 280 $r5 = tMOVr $lr, 14, $noreg 281 t2LoopEnd killed renamable $lr, %bb.4, implicit-def dead $cpsr 282 tB %bb.5, 14, $noreg 283 284 bb.5.middle.block: 285 successors: %bb.7(0x80000000) 286 liveins: $r2, $r3, $r4, $r7, $r12 287 288 tCMPr killed renamable $r4, killed renamable $r2, 14, $noreg, implicit-def $cpsr 289 $lr = tMOVr killed $r7, 14, $noreg 290 t2IT 0, 8, implicit-def $itstate 291 tPOP_RET 0, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate 292 tB %bb.7, 14, $noreg 293 294 bb.6: 295 successors: %bb.7(0x80000000) 296 liveins: $r0, $r1, $r2 297 298 $lr = tMOVr killed $r2, 14, $noreg 299 $r12 = tMOVr killed $r0, 14, $noreg 300 $r3 = tMOVr killed $r1, 14, $noreg 301 302 bb.7.while.body.preheader19: 303 successors: %bb.8(0x80000000) 304 liveins: $lr, $r3, $r12 305 306 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14, $noreg 307 renamable $r1 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 308 $lr = t2DoLoopStart renamable $lr 309 310 bb.8.while.body: 311 successors: %bb.8(0x7c000000), %bb.9(0x04000000) 312 liveins: $lr, $r0, $r1 313 314 renamable $s0 = VLDRS renamable $r1, 1, 14, $noreg :: (load 4 from %ir.scevgep3) 315 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg 316 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14, $noreg 317 VSTRS killed renamable $s0, renamable $r0, 1, 14, $noreg :: (store 4 into %ir.scevgep7) 318 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg 319 renamable $lr = t2LoopDec killed renamable $lr, 1 320 t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr 321 tB %bb.9, 14, $noreg 322 323 bb.9.while.end: 324 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc 325 326... 327