1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc void @uadd_sat(i16* noalias nocapture readonly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) { 5; CHECK-LABEL: uadd_sat: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: .save {r7, lr} 8; CHECK-NEXT: push {r7, lr} 9; CHECK-NEXT: cmp r3, #0 10; CHECK-NEXT: it eq 11; CHECK-NEXT: popeq {r7, pc} 12; CHECK-NEXT: .LBB0_1: @ %vector.ph 13; CHECK-NEXT: dlstp.16 lr, r3 14; CHECK-NEXT: .LBB0_2: @ %vector.body 15; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 16; CHECK-NEXT: vldrh.u16 q0, [r1], #16 17; CHECK-NEXT: vldrh.u16 q1, [r0], #16 18; CHECK-NEXT: vqadd.u16 q0, q1, q0 19; CHECK-NEXT: vstrh.16 q0, [r2], #16 20; CHECK-NEXT: letp lr, .LBB0_2 21; CHECK-NEXT: @ %bb.3: @ %while.end 22; CHECK-NEXT: pop {r7, pc} 23entry: 24 %cmp7 = icmp eq i32 %blockSize, 0 25 br i1 %cmp7, label %while.end, label %vector.ph 26 27vector.ph: ; preds = %entry 28 %n.rnd.up = add i32 %blockSize, 7 29 %n.vec = and i32 %n.rnd.up, -8 30 %trip.count.minus.1 = add i32 %blockSize, -1 31 br label %vector.body 32 33vector.body: ; preds = %vector.body, %vector.ph 34 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] 35 %next.gep = getelementptr i16, i16* %pSrcA, i32 %index 36 %next.gep20 = getelementptr i16, i16* %pDst, i32 %index 37 %next.gep21 = getelementptr i16, i16* %pSrcB, i32 %index 38 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize) 39 %0 = bitcast i16* %next.gep to <8 x i16>* 40 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef) 41 %1 = bitcast i16* %next.gep21 to <8 x i16>* 42 %wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef) 43 %2 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24) 44 %3 = bitcast i16* %next.gep20 to <8 x i16>* 45 call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask) 46 %index.next = add i32 %index, 8 47 %4 = icmp eq i32 %index.next, %n.vec 48 br i1 %4, label %while.end, label %vector.body 49 50while.end: ; preds = %vector.body, %entry 51 ret void 52} 53 54define arm_aapcs_vfpcc void @sadd_sat(i16* noalias nocapture readonly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) { 55; CHECK-LABEL: sadd_sat: 56; CHECK: @ %bb.0: @ %entry 57; CHECK-NEXT: .save {r7, lr} 58; CHECK-NEXT: push {r7, lr} 59; CHECK-NEXT: cmp r3, #0 60; CHECK-NEXT: it eq 61; CHECK-NEXT: popeq {r7, pc} 62; CHECK-NEXT: .LBB1_1: @ %vector.ph 63; CHECK-NEXT: dlstp.16 lr, r3 64; CHECK-NEXT: .LBB1_2: @ %vector.body 65; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 66; CHECK-NEXT: vldrh.u16 q0, [r1], #16 67; CHECK-NEXT: vldrh.u16 q1, [r0], #16 68; CHECK-NEXT: vqadd.s16 q0, q1, q0 69; CHECK-NEXT: vstrh.16 q0, [r2], #16 70; CHECK-NEXT: letp lr, .LBB1_2 71; CHECK-NEXT: @ %bb.3: @ %while.end 72; CHECK-NEXT: pop {r7, pc} 73entry: 74 %cmp7 = icmp eq i32 %blockSize, 0 75 br i1 %cmp7, label %while.end, label %vector.ph 76 77vector.ph: ; preds = %entry 78 %n.rnd.up = add i32 %blockSize, 7 79 %n.vec = and i32 %n.rnd.up, -8 80 %trip.count.minus.1 = add i32 %blockSize, -1 81 br label %vector.body 82 83vector.body: ; preds = %vector.body, %vector.ph 84 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] 85 %next.gep = getelementptr i16, i16* %pSrcA, i32 %index 86 %next.gep20 = getelementptr i16, i16* %pDst, i32 %index 87 %next.gep21 = getelementptr i16, i16* %pSrcB, i32 %index 88 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize) 89 %0 = bitcast i16* %next.gep to <8 x i16>* 90 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef) 91 %1 = bitcast i16* %next.gep21 to <8 x i16>* 92 %wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef) 93 %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24) 94 %3 = bitcast i16* %next.gep20 to <8 x i16>* 95 call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask) 96 %index.next = add i32 %index, 8 97 %4 = icmp eq i32 %index.next, %n.vec 98 br i1 %4, label %while.end, label %vector.body 99 100while.end: ; preds = %vector.body, %entry 101 ret void 102} 103 104declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) 105 106declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>) 107 108declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 109 110declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) 111 112declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>) 113