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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s
3# Check that subs isn't used during the revert because there's a cpsr use after it.
4
5--- |
6  define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
7  entry:
8    %scevgep = getelementptr i32, i32* %q, i32 -1
9    %scevgep3 = getelementptr i32, i32* %p, i32 -1
10    %start = call i32 @llvm.start.loop.iterations.i32(i32 %n)
11    %limit = lshr i32 %n, 1
12    br label %while.body
13
14  while.body:                                       ; preds = %while.body, %entry
15    %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
16    %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
17    %tmp = phi i32 [ %start, %entry ], [ %tmp2, %while.body ]
18    %scevgep7 = getelementptr i32, i32* %lsr.iv, i32 1
19    %scevgep4 = getelementptr i32, i32* %lsr.iv4, i32 1
20    %tmp1 = load i32, i32* %scevgep7, align 4
21    %tmp2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp, i32 1)
22    %half = lshr i32 %tmp1, 1
23    %cmp = icmp ult i32 %tmp, %limit
24    %res = select i1 %cmp, i32 %tmp1, i32 %half
25    store i32 %res, i32* %scevgep4, align 4
26    %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
27    %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
28    %tmp3 = icmp ne i32 %tmp2, 0
29    br i1 %tmp3, label %while.body, label %while.end
30
31  while.end:                                        ; preds = %while.body
32    ret i32 0
33  }
34
35  ; Function Attrs: noduplicate nounwind
36  declare i32 @llvm.start.loop.iterations.i32(i32) #0
37
38  ; Function Attrs: noduplicate nounwind
39  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
40
41  ; Function Attrs: nounwind
42  declare void @llvm.stackprotector(i8*, i8**) #1
43
44  attributes #0 = { noduplicate nounwind }
45  attributes #1 = { nounwind }
46
47...
48---
49name:            do_copy
50alignment:       2
51exposesReturnsTwice: false
52legalized:       false
53regBankSelected: false
54selected:        false
55failedISel:      false
56tracksRegLiveness: true
57hasWinCFI:       false
58registers:       []
59liveins:
60  - { reg: '$r0', virtual-reg: '' }
61  - { reg: '$r1', virtual-reg: '' }
62  - { reg: '$r2', virtual-reg: '' }
63frameInfo:
64  isFrameAddressTaken: false
65  isReturnAddressTaken: false
66  hasStackMap:     false
67  hasPatchPoint:   false
68  stackSize:       8
69  offsetAdjustment: 0
70  maxAlignment:    4
71  adjustsStack:    false
72  hasCalls:        false
73  stackProtector:  ''
74  maxCallFrameSize: 0
75  cvBytesOfCalleeSavedRegisters: 0
76  hasOpaqueSPAdjustment: false
77  hasVAStart:      false
78  hasMustTailInVarArgFunc: false
79  localFrameSize:  0
80  savePoint:       ''
81  restorePoint:    ''
82fixedStack:      []
83stack:
84  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
85      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
86      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
87  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
88      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
89      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
90callSites:       []
91constants:       []
92machineFunctionInfo: {}
93body:             |
94  ; CHECK-LABEL: name: do_copy
95  ; CHECK: bb.0.entry:
96  ; CHECK:   successors: %bb.1(0x80000000)
97  ; CHECK:   liveins: $lr, $r1, $r2, $r7
98  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
99  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
100  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
101  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
102  ; CHECK:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
103  ; CHECK:   renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
104  ; CHECK:   renamable $r2 = t2LSRri renamable $r0, 1, 14 /* CC::al */, $noreg, $noreg
105  ; CHECK:   $lr = tMOVr $r0, 14 /* CC::al */, $noreg
106  ; CHECK: bb.1.while.body:
107  ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
108  ; CHECK:   liveins: $lr, $r0, $r1, $r2
109  ; CHECK:   renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
110  ; CHECK:   tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
111  ; CHECK:   $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
112  ; CHECK:   t2IT 2, 8, implicit-def $itstate
113  ; CHECK:   renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
114  ; CHECK:   early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep4)
115  ; CHECK:   renamable $lr = tMOVr killed $lr, 14 /* CC::al */, $noreg
116  ; CHECK:   t2CMPri renamable $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
117  ; CHECK:   tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
118  ; CHECK:   tB %bb.2, 14 /* CC::al */, $noreg
119  ; CHECK: bb.2.while.end:
120  ; CHECK:   $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
121  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
122  bb.0.entry:
123    successors: %bb.1(0x80000000)
124    liveins: $r0, $r1, $r2, $r7, $lr
125
126    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
127    frame-setup CFI_INSTRUCTION def_cfa_offset 8
128    frame-setup CFI_INSTRUCTION offset $lr, -4
129    frame-setup CFI_INSTRUCTION offset $r7, -8
130    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
131    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
132    $lr = t2DoLoopStart renamable $r0
133    renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg
134    $lr = tMOVr $r0, 14, $noreg
135
136  bb.1.while.body:
137    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
138    liveins: $lr, $r0, $r1, $r2
139
140    renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
141    tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
142    renamable $lr = t2LoopDec killed renamable $lr, 1
143    t2IT 2, 8, implicit-def $itstate
144    renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
145    early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
146    renamable $lr = tMOVr $lr, 14, $noreg
147    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
148    tB %bb.2, 14, $noreg
149
150  bb.2.while.end:
151    $r0, dead $cpsr = tMOVi8 0, 14, $noreg
152    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
153
154...
155